diff options
| author | 2017-01-03 11:13:50 +0000 | |
|---|---|---|
| committer | 2017-01-03 11:13:51 +0000 | |
| commit | 66e3919bc42ddca40302ce5ee32e3ade248dd2b6 (patch) | |
| tree | 3800e8499317efc4b5bca06e483b2bcbd9da8d9d /compiler/utils/mips64/assembler_mips64.cc | |
| parent | 6a14c622700e088173ba909799c1e1785aeb4b34 (diff) | |
| parent | e36605910cb13da1440fb9d7a8293842a9209c97 (diff) | |
Merge "MIPS64: java.lang.String.getChars"
Diffstat (limited to 'compiler/utils/mips64/assembler_mips64.cc')
| -rw-r--r-- | compiler/utils/mips64/assembler_mips64.cc | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/compiler/utils/mips64/assembler_mips64.cc b/compiler/utils/mips64/assembler_mips64.cc index 04430b13f1..5906a71b38 100644 --- a/compiler/utils/mips64/assembler_mips64.cc +++ b/compiler/utils/mips64/assembler_mips64.cc @@ -319,6 +319,18 @@ void Mips64Assembler::Dinsu(GpuRegister rt, GpuRegister rs, int pos, int size) { EmitR(0x1f, rs, rt, static_cast<GpuRegister>(pos + size - 33), pos - 32, 0x6); } +void Mips64Assembler::Lsa(GpuRegister rd, GpuRegister rs, GpuRegister rt, int saPlusOne) { + CHECK(1 <= saPlusOne && saPlusOne <= 4) << saPlusOne; + int sa = saPlusOne - 1; + EmitR(0x0, rs, rt, rd, sa, 0x05); +} + +void Mips64Assembler::Dlsa(GpuRegister rd, GpuRegister rs, GpuRegister rt, int saPlusOne) { + CHECK(1 <= saPlusOne && saPlusOne <= 4) << saPlusOne; + int sa = saPlusOne - 1; + EmitR(0x0, rs, rt, rd, sa, 0x15); +} + void Mips64Assembler::Wsbh(GpuRegister rd, GpuRegister rt) { EmitRtd(0x1f, rt, rd, 2, 0x20); } |