Revert "Introduce a number of MSA instructions for MIPS64"

This reverts commit dcabc8b740bf3066d59348ffdf21c164d2b27cb4.


Reason:
FAILING TESTS
valgrind-test-art-host-gtest-assembler_mips64_test32
ninja: build stopped: subcommand failed.
19:36:36 ninja failed with: exit status 1
make: *** [run_soong_ui] Error 1

Change-Id: If658375528d2a0f34bb6b22b6565fab1d863b3f5

1 files changed, 0 insertions, 472 deletions

diff --git a/compiler/utils/mips64/assembler_mips64.cc b/compiler/utils/mips64/assembler_mips64.cc
index c14315a91e..39eb5893d8 100644
--- a/compiler/utils/mips64/assembler_mips64.cc
+++ b/compiler/utils/mips64/assembler_mips64.cc
@@ -184,106 +184,6 @@ void Mips64Assembler::EmitFI(int opcode, int fmt, FpuRegister ft, uint16_t imm)
   Emit(encoding);
 }
 
-void Mips64Assembler::EmitMsa3R(int operation,
-                                int df,
-                                VectorRegister wt,
-                                VectorRegister ws,
-                                VectorRegister wd,
-                                int minor_opcode) {
-  CHECK_NE(wt, kNoVectorRegister);
-  CHECK_NE(ws, kNoVectorRegister);
-  CHECK_NE(wd, kNoVectorRegister);
-  uint32_t encoding = static_cast<uint32_t>(kMsaMajorOpcode) << kOpcodeShift |
-                      operation << kMsaOperationShift |
-                      df << kDfShift |
-                      static_cast<uint32_t>(wt) << kWtShift |
-                      static_cast<uint32_t>(ws) << kWsShift |
-                      static_cast<uint32_t>(wd) << kWdShift |
-                      minor_opcode;
-  Emit(encoding);
-}
-
-void Mips64Assembler::EmitMsaBIT(int operation,
-                                 int df_m,
-                                 VectorRegister ws,
-                                 VectorRegister wd,
-                                 int minor_opcode) {
-  CHECK_NE(ws, kNoVectorRegister);
-  CHECK_NE(wd, kNoVectorRegister);
-  uint32_t encoding = static_cast<uint32_t>(kMsaMajorOpcode) << kOpcodeShift |
-                      operation << kMsaOperationShift |
-                      df_m << kDfMShift |
-                      static_cast<uint32_t>(ws) << kWsShift |
-                      static_cast<uint32_t>(wd) << kWdShift |
-                      minor_opcode;
-  Emit(encoding);
-}
-
-void Mips64Assembler::EmitMsaELM(int operation,
-                                 int df_n,
-                                 VectorRegister ws,
-                                 VectorRegister wd,
-                                 int minor_opcode) {
-  CHECK_NE(ws, kNoVectorRegister);
-  CHECK_NE(wd, kNoVectorRegister);
-  uint32_t encoding = static_cast<uint32_t>(kMsaMajorOpcode) << kOpcodeShift |
-                      operation << kMsaELMOperationShift |
-                      df_n << kDfNShift |
-                      static_cast<uint32_t>(ws) << kWsShift |
-                      static_cast<uint32_t>(wd) << kWdShift |
-                      minor_opcode;
-  Emit(encoding);
-}
-
-void Mips64Assembler::EmitMsaMI10(int s10,
-                                  GpuRegister rs,
-                                  VectorRegister wd,
-                                  int minor_opcode,
-                                  int df) {
-  CHECK_NE(rs, kNoGpuRegister);
-  CHECK_NE(wd, kNoVectorRegister);
-  CHECK(IsUint<10>(s10)) << s10;
-  uint32_t encoding = static_cast<uint32_t>(kMsaMajorOpcode) << kOpcodeShift |
-                      s10 << kS10Shift |
-                      static_cast<uint32_t>(rs) << kWsShift |
-                      static_cast<uint32_t>(wd) << kWdShift |
-                      minor_opcode << kS10MinorShift |
-                      df;
-  Emit(encoding);
-}
-
-void Mips64Assembler::EmitMsa2R(int operation,
-                                int df,
-                                VectorRegister ws,
-                                VectorRegister wd,
-                                int minor_opcode) {
-  CHECK_NE(ws, kNoVectorRegister);
-  CHECK_NE(wd, kNoVectorRegister);
-  uint32_t encoding = static_cast<uint32_t>(kMsaMajorOpcode) << kOpcodeShift |
-                      operation << kMsa2ROperationShift |
-                      df << kDf2RShift |
-                      static_cast<uint32_t>(ws) << kWsShift |
-                      static_cast<uint32_t>(wd) << kWdShift |
-                      minor_opcode;
-  Emit(encoding);
-}
-
-void Mips64Assembler::EmitMsa2RF(int operation,
-                                 int df,
-                                 VectorRegister ws,
-                                 VectorRegister wd,
-                                 int minor_opcode) {
-  CHECK_NE(ws, kNoVectorRegister);
-  CHECK_NE(wd, kNoVectorRegister);
-  uint32_t encoding = static_cast<uint32_t>(kMsaMajorOpcode) << kOpcodeShift |
-                      operation << kMsa2RFOperationShift |
-                      df << kDf2RShift |
-                      static_cast<uint32_t>(ws) << kWsShift |
-                      static_cast<uint32_t>(wd) << kWdShift |
-                      minor_opcode;
-  Emit(encoding);
-}
-
 void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
   EmitR(0, rs, rt, rd, 0, 0x21);
 }
@@ -1180,378 +1080,6 @@ void Mips64Assembler::Not(GpuRegister rd, GpuRegister rs) {
   Nor(rd, rs, ZERO);
 }
 
-// TODO: Check for MSA presence in Mips64InstructionSetFeatures for each MSA instruction.
-
-void Mips64Assembler::AndV(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x0, 0x0, wt, ws, wd, 0x1e);
-}
-
-void Mips64Assembler::OrV(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x0, 0x1, wt, ws, wd, 0x1e);
-}
-
-void Mips64Assembler::NorV(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x0, 0x2, wt, ws, wd, 0x1e);
-}
-
-void Mips64Assembler::XorV(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x0, 0x3, wt, ws, wd, 0x1e);
-}
-
-void Mips64Assembler::AddvB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x0, 0x0, wt, ws, wd, 0xe);
-}
-
-void Mips64Assembler::AddvH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x0, 0x1, wt, ws, wd, 0xe);
-}
-
-void Mips64Assembler::AddvW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x0, 0x2, wt, ws, wd, 0xe);
-}
-
-void Mips64Assembler::AddvD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x0, 0x3, wt, ws, wd, 0xe);
-}
-
-void Mips64Assembler::SubvB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x1, 0x0, wt, ws, wd, 0xe);
-}
-
-void Mips64Assembler::SubvH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x1, 0x1, wt, ws, wd, 0xe);
-}
-
-void Mips64Assembler::SubvW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x1, 0x2, wt, ws, wd, 0xe);
-}
-
-void Mips64Assembler::SubvD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x1, 0x3, wt, ws, wd, 0xe);
-}
-
-void Mips64Assembler::MulvB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x0, 0x0, wt, ws, wd, 0x12);
-}
-
-void Mips64Assembler::MulvH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x0, 0x1, wt, ws, wd, 0x12);
-}
-
-void Mips64Assembler::MulvW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x0, 0x2, wt, ws, wd, 0x12);
-}
-
-void Mips64Assembler::MulvD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x0, 0x3, wt, ws, wd, 0x12);
-}
-
-void Mips64Assembler::Div_sB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x4, 0x0, wt, ws, wd, 0x12);
-}
-
-void Mips64Assembler::Div_sH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x4, 0x1, wt, ws, wd, 0x12);
-}
-
-void Mips64Assembler::Div_sW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x4, 0x2, wt, ws, wd, 0x12);
-}
-
-void Mips64Assembler::Div_sD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x4, 0x3, wt, ws, wd, 0x12);
-}
-
-void Mips64Assembler::Div_uB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x5, 0x0, wt, ws, wd, 0x12);
-}
-
-void Mips64Assembler::Div_uH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x5, 0x1, wt, ws, wd, 0x12);
-}
-
-void Mips64Assembler::Div_uW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x5, 0x2, wt, ws, wd, 0x12);
-}
-
-void Mips64Assembler::Div_uD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x5, 0x3, wt, ws, wd, 0x12);
-}
-
-void Mips64Assembler::Mod_sB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x6, 0x0, wt, ws, wd, 0x12);
-}
-
-void Mips64Assembler::Mod_sH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x6, 0x1, wt, ws, wd, 0x12);
-}
-
-void Mips64Assembler::Mod_sW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x6, 0x2, wt, ws, wd, 0x12);
-}
-
-void Mips64Assembler::Mod_sD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x6, 0x3, wt, ws, wd, 0x12);
-}
-
-void Mips64Assembler::Mod_uB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x7, 0x0, wt, ws, wd, 0x12);
-}
-
-void Mips64Assembler::Mod_uH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x7, 0x1, wt, ws, wd, 0x12);
-}
-
-void Mips64Assembler::Mod_uW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x7, 0x2, wt, ws, wd, 0x12);
-}
-
-void Mips64Assembler::Mod_uD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x7, 0x3, wt, ws, wd, 0x12);
-}
-
-void Mips64Assembler::FaddW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x0, 0x0, wt, ws, wd, 0x1b);
-}
-
-void Mips64Assembler::FaddD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x0, 0x1, wt, ws, wd, 0x1b);
-}
-
-void Mips64Assembler::FsubW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x0, 0x2, wt, ws, wd, 0x1b);
-}
-
-void Mips64Assembler::FsubD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x0, 0x3, wt, ws, wd, 0x1b);
-}
-
-void Mips64Assembler::FmulW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x1, 0x0, wt, ws, wd, 0x1b);
-}
-
-void Mips64Assembler::FmulD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x1, 0x1, wt, ws, wd, 0x1b);
-}
-
-void Mips64Assembler::FdivW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x1, 0x2, wt, ws, wd, 0x1b);
-}
-
-void Mips64Assembler::FdivD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x1, 0x3, wt, ws, wd, 0x1b);
-}
-
-void Mips64Assembler::Ffint_sW(VectorRegister wd, VectorRegister ws) {
-  EmitMsa2RF(0x19e, 0x0, ws, wd, 0x1e);
-}
-
-void Mips64Assembler::Ffint_sD(VectorRegister wd, VectorRegister ws) {
-  EmitMsa2RF(0x19e, 0x1, ws, wd, 0x1e);
-}
-
-void Mips64Assembler::Ftint_sW(VectorRegister wd, VectorRegister ws) {
-  EmitMsa2RF(0x19c, 0x0, ws, wd, 0x1e);
-}
-
-void Mips64Assembler::Ftint_sD(VectorRegister wd, VectorRegister ws) {
-  EmitMsa2RF(0x19c, 0x1, ws, wd, 0x1e);
-}
-
-void Mips64Assembler::SllB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x0, 0x0, wt, ws, wd, 0xd);
-}
-
-void Mips64Assembler::SllH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x0, 0x1, wt, ws, wd, 0xd);
-}
-
-void Mips64Assembler::SllW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x0, 0x2, wt, ws, wd, 0xd);
-}
-
-void Mips64Assembler::SllD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x0, 0x3, wt, ws, wd, 0xd);
-}
-
-void Mips64Assembler::SraB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x1, 0x0, wt, ws, wd, 0xd);
-}
-
-void Mips64Assembler::SraH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x1, 0x1, wt, ws, wd, 0xd);
-}
-
-void Mips64Assembler::SraW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x1, 0x2, wt, ws, wd, 0xd);
-}
-
-void Mips64Assembler::SraD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x1, 0x3, wt, ws, wd, 0xd);
-}
-
-void Mips64Assembler::SrlB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x2, 0x0, wt, ws, wd, 0xd);
-}
-
-void Mips64Assembler::SrlH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x2, 0x1, wt, ws, wd, 0xd);
-}
-
-void Mips64Assembler::SrlW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x2, 0x2, wt, ws, wd, 0xd);
-}
-
-void Mips64Assembler::SrlD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
-  EmitMsa3R(0x2, 0x3, wt, ws, wd, 0xd);
-}
-
-void Mips64Assembler::SlliB(VectorRegister wd, VectorRegister ws, int shamt3) {
-  CHECK(IsUint<3>(shamt3)) << shamt3;
-  EmitMsaBIT(0x0, shamt3 | kMsaDfMByteMask, ws, wd, 0x9);
-}
-
-void Mips64Assembler::SlliH(VectorRegister wd, VectorRegister ws, int shamt4) {
-  CHECK(IsUint<4>(shamt4)) << shamt4;
-  EmitMsaBIT(0x0, shamt4 | kMsaDfMHalfwordMask, ws, wd, 0x9);
-}
-
-void Mips64Assembler::SlliW(VectorRegister wd, VectorRegister ws, int shamt5) {
-  CHECK(IsUint<5>(shamt5)) << shamt5;
-  EmitMsaBIT(0x0, shamt5 | kMsaDfMWordMask, ws, wd, 0x9);
-}
-
-void Mips64Assembler::SlliD(VectorRegister wd, VectorRegister ws, int shamt6) {
-  CHECK(IsUint<6>(shamt6)) << shamt6;
-  EmitMsaBIT(0x0, shamt6 | kMsaDfMDoublewordMask, ws, wd, 0x9);
-}
-
-void Mips64Assembler::SraiB(VectorRegister wd, VectorRegister ws, int shamt3) {
-  CHECK(IsUint<3>(shamt3)) << shamt3;
-  EmitMsaBIT(0x1, shamt3 | kMsaDfMByteMask, ws, wd, 0x9);
-}
-
-void Mips64Assembler::SraiH(VectorRegister wd, VectorRegister ws, int shamt4) {
-  CHECK(IsUint<4>(shamt4)) << shamt4;
-  EmitMsaBIT(0x1, shamt4 | kMsaDfMHalfwordMask, ws, wd, 0x9);
-}
-
-void Mips64Assembler::SraiW(VectorRegister wd, VectorRegister ws, int shamt5) {
-  CHECK(IsUint<5>(shamt5)) << shamt5;
-  EmitMsaBIT(0x1, shamt5 | kMsaDfMWordMask, ws, wd, 0x9);
-}
-
-void Mips64Assembler::SraiD(VectorRegister wd, VectorRegister ws, int shamt6) {
-  CHECK(IsUint<6>(shamt6)) << shamt6;
-  EmitMsaBIT(0x1, shamt6 | kMsaDfMDoublewordMask, ws, wd, 0x9);
-}
-
-void Mips64Assembler::SrliB(VectorRegister wd, VectorRegister ws, int shamt3) {
-  CHECK(IsUint<3>(shamt3)) << shamt3;
-  EmitMsaBIT(0x2, shamt3 | kMsaDfMByteMask, ws, wd, 0x9);
-}
-
-void Mips64Assembler::SrliH(VectorRegister wd, VectorRegister ws, int shamt4) {
-  CHECK(IsUint<4>(shamt4)) << shamt4;
-  EmitMsaBIT(0x2, shamt4 | kMsaDfMHalfwordMask, ws, wd, 0x9);
-}
-
-void Mips64Assembler::SrliW(VectorRegister wd, VectorRegister ws, int shamt5) {
-  CHECK(IsUint<5>(shamt5)) << shamt5;
-  EmitMsaBIT(0x2, shamt5 | kMsaDfMWordMask, ws, wd, 0x9);
-}
-
-void Mips64Assembler::SrliD(VectorRegister wd, VectorRegister ws, int shamt6) {
-  CHECK(IsUint<6>(shamt6)) << shamt6;
-  EmitMsaBIT(0x2, shamt6 | kMsaDfMDoublewordMask, ws, wd, 0x9);
-}
-
-void Mips64Assembler::MoveV(VectorRegister wd, VectorRegister ws) {
-  EmitMsaBIT(0x1, 0x3e, ws, wd, 0x19);
-}
-
-void Mips64Assembler::SplatiB(VectorRegister wd, VectorRegister ws, int n4) {
-  CHECK(IsUint<4>(n4)) << n4;
-  EmitMsaELM(0x1, n4 | kMsaDfNByteMask, ws, wd, 0x19);
-}
-
-void Mips64Assembler::SplatiH(VectorRegister wd, VectorRegister ws, int n3) {
-  CHECK(IsUint<3>(n3)) << n3;
-  EmitMsaELM(0x1, n3 | kMsaDfNHalfwordMask, ws, wd, 0x19);
-}
-
-void Mips64Assembler::SplatiW(VectorRegister wd, VectorRegister ws, int n2) {
-  CHECK(IsUint<2>(n2)) << n2;
-  EmitMsaELM(0x1, n2 | kMsaDfNWordMask, ws, wd, 0x19);
-}
-
-void Mips64Assembler::SplatiD(VectorRegister wd, VectorRegister ws, int n1) {
-  CHECK(IsUint<1>(n1)) << n1;
-  EmitMsaELM(0x1, n1 | kMsaDfNDoublewordMask, ws, wd, 0x19);
-}
-
-void Mips64Assembler::FillB(VectorRegister wd, GpuRegister rs) {
-  EmitMsa2R(0xc0, 0x0, static_cast<VectorRegister>(rs), wd, 0x1e);
-}
-
-void Mips64Assembler::FillH(VectorRegister wd, GpuRegister rs) {
-  EmitMsa2R(0xc0, 0x1, static_cast<VectorRegister>(rs), wd, 0x1e);
-}
-
-void Mips64Assembler::FillW(VectorRegister wd, GpuRegister rs) {
-  EmitMsa2R(0xc0, 0x2, static_cast<VectorRegister>(rs), wd, 0x1e);
-}
-
-void Mips64Assembler::FillD(VectorRegister wd, GpuRegister rs) {
-  EmitMsa2R(0xc0, 0x3, static_cast<VectorRegister>(rs), wd, 0x1e);
-}
-
-void Mips64Assembler::LdB(VectorRegister wd, GpuRegister rs, int offset) {
-  CHECK(IsInt<10>(offset)) << offset;
-  EmitMsaMI10(offset & kMsaS10Mask, rs, wd, 0x8, 0x0);
-}
-
-void Mips64Assembler::LdH(VectorRegister wd, GpuRegister rs, int offset) {
-  CHECK(IsInt<11>(offset)) << offset;
-  CHECK_ALIGNED(offset, kMips64HalfwordSize);
-  EmitMsaMI10((offset >> TIMES_2) & kMsaS10Mask, rs, wd, 0x8, 0x1);
-}
-
-void Mips64Assembler::LdW(VectorRegister wd, GpuRegister rs, int offset) {
-  CHECK(IsInt<12>(offset)) << offset;
-  CHECK_ALIGNED(offset, kMips64WordSize);
-  EmitMsaMI10((offset >> TIMES_4) & kMsaS10Mask, rs, wd, 0x8, 0x2);
-}
-
-void Mips64Assembler::LdD(VectorRegister wd, GpuRegister rs, int offset) {
-  CHECK(IsInt<13>(offset)) << offset;
-  CHECK_ALIGNED(offset, kMips64DoublewordSize);
-  EmitMsaMI10((offset >> TIMES_8) & kMsaS10Mask, rs, wd, 0x8, 0x3);
-}
-
-void Mips64Assembler::StB(VectorRegister wd, GpuRegister rs, int offset) {
-  CHECK(IsInt<10>(offset)) << offset;
-  EmitMsaMI10(offset & kMsaS10Mask, rs, wd, 0x9, 0x0);
-}
-
-void Mips64Assembler::StH(VectorRegister wd, GpuRegister rs, int offset) {
-  CHECK(IsInt<11>(offset)) << offset;
-  CHECK_ALIGNED(offset, kMips64HalfwordSize);
-  EmitMsaMI10((offset >> TIMES_2) & kMsaS10Mask, rs, wd, 0x9, 0x1);
-}
-
-void Mips64Assembler::StW(VectorRegister wd, GpuRegister rs, int offset) {
-  CHECK(IsInt<12>(offset)) << offset;
-  CHECK_ALIGNED(offset, kMips64WordSize);
-  EmitMsaMI10((offset >> TIMES_4) & kMsaS10Mask, rs, wd, 0x9, 0x2);
-}
-
-void Mips64Assembler::StD(VectorRegister wd, GpuRegister rs, int offset) {
-  CHECK(IsInt<13>(offset)) << offset;
-  CHECK_ALIGNED(offset, kMips64DoublewordSize);
-  EmitMsaMI10((offset >> TIMES_8) & kMsaS10Mask, rs, wd, 0x9, 0x3);
-}
-
 void Mips64Assembler::LoadConst32(GpuRegister rd, int32_t value) {
   TemplateLoadConst32(this, rd, value);
 }