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| author | 2015-11-18 12:26:08 -0800 | |
|---|---|---|
| committer | 2015-11-30 15:04:51 -0800 | |
| commit | 70014c8af8d3a20c2987c308788bc86671bc39e9 (patch) | |
| tree | bff8dd184ff7d753ee77802b973ac91fc8bff86b /compiler/utils/mips/assembler_mips.h | |
| parent | 1850cb43dbddbc655a6f990a7d475587fa9d6659 (diff) | |
MIPS32: java.lang.*.reverse
- int java.lang.Integer.reverse(int)
- long java.lang.Long.reverse(long)
Change-Id: I18d0f784b9e4bffdc1bda3604f4ed7d3c57b8d68
Diffstat (limited to 'compiler/utils/mips/assembler_mips.h')
| -rw-r--r-- | compiler/utils/mips/assembler_mips.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/compiler/utils/mips/assembler_mips.h b/compiler/utils/mips/assembler_mips.h index 1ef0992dac..6a37cc9b1c 100644 --- a/compiler/utils/mips/assembler_mips.h +++ b/compiler/utils/mips/assembler_mips.h @@ -136,6 +136,7 @@ class MipsAssembler FINAL : public Assembler { void Seb(Register rd, Register rt); // R2+ void Seh(Register rd, Register rt); // R2+ void Wsbh(Register rd, Register rt); // R2+ + void Bitswap(Register rd, Register rt); // R6 void Sll(Register rd, Register rt, int shamt); void Srl(Register rd, Register rt, int shamt); |