diff options
| author | 2016-03-17 17:21:45 -0700 | |
|---|---|---|
| committer | 2016-03-21 15:23:42 -0700 | |
| commit | 51aff3a6564303cab0b7ac82495b4e2e349c6ff3 (patch) | |
| tree | 783344fdc2f757a8fce4ac1b565e2b2798415d2d /compiler/utils/mips/assembler_mips.h | |
| parent | 6a329292736c3dd74e9c8cb319c2a233d07fe524 (diff) | |
MIPS32: Implement UnsafeCASInt and UnsafeCASObject intrinsics.
Change-Id: Ie871763b9a36075fd3d70ee6e2e241ae1ccc36cf
Diffstat (limited to 'compiler/utils/mips/assembler_mips.h')
| -rw-r--r-- | compiler/utils/mips/assembler_mips.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/compiler/utils/mips/assembler_mips.h b/compiler/utils/mips/assembler_mips.h index a7179fd1dc..ffac4c4168 100644 --- a/compiler/utils/mips/assembler_mips.h +++ b/compiler/utils/mips/assembler_mips.h @@ -191,6 +191,11 @@ class MipsAssembler FINAL : public Assembler { void Swl(Register rt, Register rs, uint16_t imm16); void Swr(Register rt, Register rs, uint16_t imm16); + void LlR2(Register rt, Register base, int16_t imm16 = 0); + void ScR2(Register rt, Register base, int16_t imm16 = 0); + void LlR6(Register rt, Register base, int16_t imm9 = 0); + void ScR6(Register rt, Register base, int16_t imm9 = 0); + void Slt(Register rd, Register rs, Register rt); void Sltu(Register rd, Register rs, Register rt); void Slti(Register rt, Register rs, uint16_t imm16); |