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author Treehugger Robot <treehugger-gerrit@google.com> 2017-07-13 20:00:20 +0000
committer Gerrit Code Review <noreply-gerritcodereview@google.com> 2017-07-13 20:00:20 +0000
commit99d50e80f3d186c9ae19736b9b224ee319d936f9 (patch)
treefd6c930adcb2f55f3aa16201f16917fcdb8a34fb /compiler/utils/mips/assembler_mips.cc
parent2a77a6341e4db51ca372460b64051b55509fc2f6 (diff)
parent51765b098301fff1897361b2d1a21af356d9d6d8 (diff)
Merge "MIPS32: ART Vectorizer"
Diffstat (limited to 'compiler/utils/mips/assembler_mips.cc')
-rw-r--r--compiler/utils/mips/assembler_mips.cc11
1 files changed, 11 insertions, 0 deletions
diff --git a/compiler/utils/mips/assembler_mips.cc b/compiler/utils/mips/assembler_mips.cc
index 44b9bb4eb9..c581f1c58f 100644
--- a/compiler/utils/mips/assembler_mips.cc
+++ b/compiler/utils/mips/assembler_mips.cc
@@ -2904,6 +2904,17 @@ void MipsAssembler::IlvrD(VectorRegister wd, VectorRegister ws, VectorRegister w
static_cast<FRegister>(wt));
}
+void MipsAssembler::ReplicateFPToVectorRegister(VectorRegister dst,
+ FRegister src,
+ bool is_double) {
+ // Float or double in FPU register Fx can be considered as 0th element in vector register Wx.
+ if (is_double) {
+ SplatiD(dst, static_cast<VectorRegister>(src), 0);
+ } else {
+ SplatiW(dst, static_cast<VectorRegister>(src), 0);
+ }
+}
+
void MipsAssembler::LoadConst32(Register rd, int32_t value) {
if (IsUint<16>(value)) {
// Use OR with (unsigned) immediate to encode 16b unsigned int.