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| author | 2015-12-05 02:08:06 +0000 | |
|---|---|---|
| committer | 2015-12-05 02:08:06 +0000 | |
| commit | 5bde68ff34aeb84a1fc84734bcd31471d9a9717c (patch) | |
| tree | ec3e56c3853a785ddb0310c8c13f6bd2ccaed818 /compiler/utils/mips/assembler_mips.cc | |
| parent | fdacff89f5b5c276254beb5643fda5df16ba7dd3 (diff) | |
| parent | e16ce5a52da4fcbb8c6b5d1ec696863fcf113409 (diff) | |
Merge "MIPS32: Bit rotation intrinsics"
Diffstat (limited to 'compiler/utils/mips/assembler_mips.cc')
| -rw-r--r-- | compiler/utils/mips/assembler_mips.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/compiler/utils/mips/assembler_mips.cc b/compiler/utils/mips/assembler_mips.cc index 5a4de82eaf..42f21e603d 100644 --- a/compiler/utils/mips/assembler_mips.cc +++ b/compiler/utils/mips/assembler_mips.cc @@ -387,6 +387,10 @@ void MipsAssembler::Srlv(Register rd, Register rt, Register rs) { EmitR(0, rs, rt, rd, 0, 0x06); } +void MipsAssembler::Rotrv(Register rd, Register rt, Register rs) { + EmitR(0, rs, rt, rd, 1, 0x06); +} + void MipsAssembler::Srav(Register rd, Register rt, Register rs) { EmitR(0, rs, rt, rd, 0, 0x07); } |