riscv64: Enable JNI compiler.

Implement the required `WriteCIE()`, fix a bug in the
`art_jni_dlsym_lookup_critical_stub`, fix reference loads
to be zero-extended and enable the JNI compiler for riscv64.

Test: m test-art-host-gtest
Test: testrunner.py --host --optimizing
Test: run-gtests.sh
Test: testrunner.py --target --64 --ndebug --prebuild --no-prebuild -t 178
Test: # Edit `run-test` to disable checker, then
      testrunner.py --target --64 --ndebug --cdex-none --optimizing
      # 7 tests fail (pre-existing failures): 004-StackWalk, 137-cfi,
      # 2042-reference-processing, 597-deopt-busy-loop, 629-vdex-speed,
      # 638-checker-inline-cache-intrinsic and 661-oat-writer-layout.
Test: aosp_cf_riscv64_phone-userdebug boots without crashes.
Bug: 283082089
Change-Id: Ifd47098b7428919b601dd22a130ad1bd51ae516d

1 files changed, 6 insertions, 1 deletions

diff --git a/compiler/utils/jni_macro_assembler.h b/compiler/utils/jni_macro_assembler.h
index 286c378670..2d51439ee8 100644
--- a/compiler/utils/jni_macro_assembler.h
+++ b/compiler/utils/jni_macro_assembler.h
@@ -129,9 +129,14 @@ class JNIMacroAssembler : public DeletableArenaObject<kArenaAllocAssembler> {
   // Load routines
   virtual void Load(ManagedRegister dest, FrameOffset src, size_t size) = 0;
   virtual void Load(ManagedRegister dest, ManagedRegister base, MemberOffset offs, size_t size) = 0;
-
   virtual void LoadRawPtrFromThread(ManagedRegister dest, ThreadOffset<kPointerSize> offs) = 0;
 
+  // Load reference from a `GcRoot<>`. The default is to load as `jint`. Some architectures
+  // (say, RISC-V) override this to provide a different sign- or zero-extension.
+  virtual void LoadGcRootWithoutReadBarrier(ManagedRegister dest,
+                                            ManagedRegister base,
+                                            MemberOffset offs);
+
   // Copying routines
 
   // Move arguments from `srcs` locations to `dests` locations.