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| author | 2016-07-11 14:00:46 +0100 | |
|---|---|---|
| committer | 2016-07-19 09:41:31 +0000 | |
| commit | 2e4fcc99c12d09c47eb64828169211ce8c5a9a8d (patch) | |
| tree | 126d7a03e7efbcd09395f393cd19c19d64c17fdf /compiler/utils/arm/assembler_thumb2.cc | |
| parent | 4c489f48ef432126b8e7a84b61c1c13a7514c085 (diff) | |
ARM: Fix shifted register offset mem address mode for load signed.
For example 'ldrsh r0, [sp, r1, LSL #2]' previously
was assembled as 'ldrh'.
Test: New test in assembler_thumb2_test.cc .
Change-Id: I1d30724f0c2745b131876bffefdc0a780d76f6a1
Diffstat (limited to 'compiler/utils/arm/assembler_thumb2.cc')
| -rw-r--r-- | compiler/utils/arm/assembler_thumb2.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/compiler/utils/arm/assembler_thumb2.cc b/compiler/utils/arm/assembler_thumb2.cc index 8747dad5e5..353c729249 100644 --- a/compiler/utils/arm/assembler_thumb2.cc +++ b/compiler/utils/arm/assembler_thumb2.cc @@ -2456,6 +2456,9 @@ void Thumb2Assembler::EmitLoadStore(Condition cond, } else if (!byte) { encoding |= B22; } + if (load && is_signed && (byte || half)) { + encoding |= B24; + } Emit32(encoding); } else { // 16 bit register offset. |