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| author | 2016-06-13 14:42:27 +0100 | |
|---|---|---|
| committer | 2016-06-28 13:29:29 +0000 | |
| commit | e652c122d8cc9697d368b9ceada9b377d091e4fd (patch) | |
| tree | 699f7f7bc88ff28d2b8f8e735ea48693aa653c95 /compiler/utils/arm/assembler_arm32.cc | |
| parent | ca7399a1d7b3c92d73322adf54187fde31eee1bd (diff) | |
ARM assembler support for VCNT and VPADDL.
Test: Gtest assembler_thumb2_test.
Change-Id: I8a0e47da746e1c67650cb68196a9f661deed7383
Diffstat (limited to 'compiler/utils/arm/assembler_arm32.cc')
| -rw-r--r-- | compiler/utils/arm/assembler_arm32.cc | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/compiler/utils/arm/assembler_arm32.cc b/compiler/utils/arm/assembler_arm32.cc index 0a227b21cd..6f7119d578 100644 --- a/compiler/utils/arm/assembler_arm32.cc +++ b/compiler/utils/arm/assembler_arm32.cc @@ -1264,6 +1264,31 @@ void Arm32Assembler::vmstat(Condition cond) { // VMRS APSR_nzcv, FPSCR Emit(encoding); } +void Arm32Assembler::vcntd(DRegister dd, DRegister dm) { + uint32_t encoding = (B31 | B30 | B29 | B28 | B25 | B24 | B23 | B21 | B20) | + ((static_cast<int32_t>(dd) >> 4) * B22) | + ((static_cast<uint32_t>(dd) & 0xf) * B12) | + (B10 | B8) | + ((static_cast<int32_t>(dm) >> 4) * B5) | + (static_cast<uint32_t>(dm) & 0xf); + + Emit(encoding); +} + +void Arm32Assembler::vpaddld(DRegister dd, DRegister dm, int32_t size, bool is_unsigned) { + CHECK(size == 8 || size == 16 || size == 32) << size; + uint32_t encoding = (B31 | B30 | B29 | B28 | B25 | B24 | B23 | B21 | B20) | + ((static_cast<uint32_t>(size >> 4) & 0x3) * B18) | + ((static_cast<int32_t>(dd) >> 4) * B22) | + ((static_cast<uint32_t>(dd) & 0xf) * B12) | + (B9) | + (is_unsigned ? B7 : 0) | + ((static_cast<int32_t>(dm) >> 4) * B5) | + (static_cast<uint32_t>(dm) & 0xf); + + Emit(encoding); +} + void Arm32Assembler::svc(uint32_t imm24) { CHECK(IsUint<24>(imm24)) << imm24; |