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| author | 2015-07-30 15:07:22 +0100 | |
|---|---|---|
| committer | 2015-09-01 10:10:37 +0100 | |
| commit | 73cf0fb75de2a449ce4fe329b5f1fb42eef1372f (patch) | |
| tree | d5b0957414c355254babfcd1a797ce87a0eb85a2 /compiler/utils/arm/assembler_arm.cc | |
| parent | 9ee5d6cdc14ac94b64ea1961bf221bad48746929 (diff) | |
ART: Add 16-bit Thumb2 ROR, NEGS and CMP for high registers.
Also clean up the usage of set_cc flag. Define a SetCc
enumeration that specifies whether to set or keep condition
codes or whether we don't care and a 16-bit instruction
should be selected if one exists.
This reduces the size of Nexus 5 boot.oat by 44KiB (when
compiled with Optimizing which is not the default yet).
Change-Id: I047072dc197ea678bf2019c01bcb28943fa9b604
Diffstat (limited to 'compiler/utils/arm/assembler_arm.cc')
| -rw-r--r-- | compiler/utils/arm/assembler_arm.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/compiler/utils/arm/assembler_arm.cc b/compiler/utils/arm/assembler_arm.cc index 0e3e08c2da..807bedaa04 100644 --- a/compiler/utils/arm/assembler_arm.cc +++ b/compiler/utils/arm/assembler_arm.cc @@ -137,10 +137,14 @@ uint32_t ShifterOperand::encodingThumb() const { if (rs_ == kNoRegister) { // Immediate shift. if (shift_ == RRX) { + DCHECK_EQ(immed_, 0u); // RRX is encoded as an ROR with imm 0. return ROR << 4 | static_cast<uint32_t>(rm_); } else { - uint32_t imm3 = immed_ >> 2; + DCHECK((1 <= immed_ && immed_ <= 31) || + (immed_ == 0u && shift_ == LSL) || + (immed_ == 32u && (shift_ == ASR || shift_ == LSR))); + uint32_t imm3 = (immed_ >> 2) & 7 /* 0b111*/; uint32_t imm2 = immed_ & 3U /* 0b11 */; return imm3 << 12 | imm2 << 6 | shift_ << 4 | |