diff options
| author | 2023-09-05 15:38:09 +0000 | |
|---|---|---|
| committer | 2023-09-06 08:24:27 +0000 | |
| commit | af81d552ec0f1d7967c27143046f91d79419b910 (patch) | |
| tree | a5b0385c468d429163cdab484998e3519c75ff2e /compiler/optimizing | |
| parent | b01acbe6bf47e03894cac5cd433c84f81e8d3f5d (diff) | |
riscv64: Fix codegen for 32-bit integer HMul.
Make sure the result is correctly sign-extended to 64 bits.
Test: m test-art-host-gtest
Bug: 283082089
Change-Id: Ia96b4afb3f6a57652ee7ab05e52a690507798e31
Diffstat (limited to 'compiler/optimizing')
| -rw-r--r-- | compiler/optimizing/code_generator_riscv64.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/compiler/optimizing/code_generator_riscv64.cc b/compiler/optimizing/code_generator_riscv64.cc index fa5f65fc62..f2b9286246 100644 --- a/compiler/optimizing/code_generator_riscv64.cc +++ b/compiler/optimizing/code_generator_riscv64.cc @@ -2405,6 +2405,11 @@ void InstructionCodeGeneratorRISCV64::VisitMul(HMul* instruction) { LocationSummary* locations = instruction->GetLocations(); switch (instruction->GetResultType()) { case DataType::Type::kInt32: + __ Mulw(locations->Out().AsRegister<XRegister>(), + locations->InAt(0).AsRegister<XRegister>(), + locations->InAt(1).AsRegister<XRegister>()); + break; + case DataType::Type::kInt64: __ Mul(locations->Out().AsRegister<XRegister>(), locations->InAt(0).AsRegister<XRegister>(), |