diff options
| author | 2016-02-17 16:56:49 +0000 | |
|---|---|---|
| committer | 2016-02-17 16:56:49 +0000 | |
| commit | 9ee1f0c6a67729cabcf3697fc68fe4e98da55f64 (patch) | |
| tree | 6c703f665a79acf717612fa4ccce7a48c846af89 /compiler/optimizing | |
| parent | 631d9ef435d3015b2d14ef5a47fff68c2431c126 (diff) | |
| parent | 32ca375a5f9dcd010bafa84f829339b6b612b844 (diff) | |
Merge "Fix uses of art::HCompare::IsGtBias on MIPS32 and MIPS64."
Diffstat (limited to 'compiler/optimizing')
| -rw-r--r-- | compiler/optimizing/code_generator_mips.cc | 3 | ||||
| -rw-r--r-- | compiler/optimizing/code_generator_mips64.cc | 6 |
2 files changed, 4 insertions, 5 deletions
diff --git a/compiler/optimizing/code_generator_mips.cc b/compiler/optimizing/code_generator_mips.cc index ad3e988b54..c500ea4408 100644 --- a/compiler/optimizing/code_generator_mips.cc +++ b/compiler/optimizing/code_generator_mips.cc @@ -2107,7 +2107,6 @@ void InstructionCodeGeneratorMIPS::VisitCompare(HCompare* instruction) { LocationSummary* locations = instruction->GetLocations(); Register res = locations->Out().AsRegister<Register>(); Primitive::Type in_type = instruction->InputAt(0)->GetType(); - bool gt_bias = instruction->IsGtBias(); bool isR6 = codegen_->GetInstructionSetFeatures().IsR6(); // 0 if: left == right @@ -2141,6 +2140,7 @@ void InstructionCodeGeneratorMIPS::VisitCompare(HCompare* instruction) { } case Primitive::kPrimFloat: { + bool gt_bias = instruction->IsGtBias(); FRegister lhs = locations->InAt(0).AsFpuRegister<FRegister>(); FRegister rhs = locations->InAt(1).AsFpuRegister<FRegister>(); MipsLabel done; @@ -2180,6 +2180,7 @@ void InstructionCodeGeneratorMIPS::VisitCompare(HCompare* instruction) { break; } case Primitive::kPrimDouble: { + bool gt_bias = instruction->IsGtBias(); FRegister lhs = locations->InAt(0).AsFpuRegister<FRegister>(); FRegister rhs = locations->InAt(1).AsFpuRegister<FRegister>(); MipsLabel done; diff --git a/compiler/optimizing/code_generator_mips64.cc b/compiler/optimizing/code_generator_mips64.cc index 119084e026..e3a44f1c96 100644 --- a/compiler/optimizing/code_generator_mips64.cc +++ b/compiler/optimizing/code_generator_mips64.cc @@ -1727,7 +1727,6 @@ void InstructionCodeGeneratorMIPS64::VisitCompare(HCompare* instruction) { LocationSummary* locations = instruction->GetLocations(); GpuRegister res = locations->Out().AsRegister<GpuRegister>(); Primitive::Type in_type = instruction->InputAt(0)->GetType(); - bool gt_bias = instruction->IsGtBias(); // 0 if: left == right // 1 if: left > right @@ -1769,7 +1768,7 @@ void InstructionCodeGeneratorMIPS64::VisitCompare(HCompare* instruction) { __ CmpEqS(FTMP, lhs, rhs); __ LoadConst32(res, 0); __ Bc1nez(FTMP, &done); - if (gt_bias) { + if (instruction->IsGtBias()) { __ CmpLtS(FTMP, lhs, rhs); __ LoadConst32(res, -1); __ Bc1nez(FTMP, &done); @@ -1791,7 +1790,7 @@ void InstructionCodeGeneratorMIPS64::VisitCompare(HCompare* instruction) { __ CmpEqD(FTMP, lhs, rhs); __ LoadConst32(res, 0); __ Bc1nez(FTMP, &done); - if (gt_bias) { + if (instruction->IsGtBias()) { __ CmpLtD(FTMP, lhs, rhs); __ LoadConst32(res, -1); __ Bc1nez(FTMP, &done); @@ -4258,4 +4257,3 @@ void InstructionCodeGeneratorMIPS64::VisitClassTableGet(HClassTableGet*) { } // namespace mips64 } // namespace art - |