diff options
| author | 2022-09-28 23:23:43 -0700 | |
|---|---|---|
| committer | 2022-09-29 15:25:58 +0000 | |
| commit | 88ccd92e57804ed958dec9da0fc8b67b924b3db7 (patch) | |
| tree | 27a64f02cd5377f1fb7c9bf0ec83e793700045e2 /compiler/optimizing | |
| parent | 3a60d011496dd5281410ee416b8b82cb94f4f599 (diff) | |
Make callee-saved registers behave according to kReserveMarkingRegister
We were mistakenly blocking the marking register and refreshing it, but
didn't remove it from callee-saved registers list when CC GC is not
being used, leading to crashes.
Test: art/test/testrnunner/testrunner.py --target --32 --jit
Change-Id: I33e18c900042fd1dfb1f75512868c895fd83c1e1
Diffstat (limited to 'compiler/optimizing')
| -rw-r--r-- | compiler/optimizing/code_generator_arm64.h | 4 | ||||
| -rw-r--r-- | compiler/optimizing/code_generator_arm_vixl.h | 2 |
2 files changed, 2 insertions, 4 deletions
diff --git a/compiler/optimizing/code_generator_arm64.h b/compiler/optimizing/code_generator_arm64.h index 5bf12db078..66e8471483 100644 --- a/compiler/optimizing/code_generator_arm64.h +++ b/compiler/optimizing/code_generator_arm64.h @@ -114,9 +114,7 @@ inline Location FixedTempLocation() { const vixl::aarch64::CPURegList callee_saved_core_registers( vixl::aarch64::CPURegister::kRegister, vixl::aarch64::kXRegSize, - ((gUseReadBarrier && kUseBakerReadBarrier) - ? vixl::aarch64::x21.GetCode() - : vixl::aarch64::x20.GetCode()), + (kReserveMarkingRegister ? vixl::aarch64::x21.GetCode() : vixl::aarch64::x20.GetCode()), vixl::aarch64::x30.GetCode()); const vixl::aarch64::CPURegList callee_saved_fp_registers(vixl::aarch64::CPURegister::kVRegister, vixl::aarch64::kDRegSize, diff --git a/compiler/optimizing/code_generator_arm_vixl.h b/compiler/optimizing/code_generator_arm_vixl.h index fc5fc489fe..e5b31cf9d8 100644 --- a/compiler/optimizing/code_generator_arm_vixl.h +++ b/compiler/optimizing/code_generator_arm_vixl.h @@ -84,7 +84,7 @@ static const vixl::aarch32::RegisterList kCoreCalleeSaves = vixl::aarch32::Regis vixl::aarch32::r6, vixl::aarch32::r7), // Do not consider r8 as a callee-save register with Baker read barriers. - ((gUseReadBarrier && kUseBakerReadBarrier) + (kReserveMarkingRegister ? vixl::aarch32::RegisterList() : vixl::aarch32::RegisterList(vixl::aarch32::r8)), vixl::aarch32::RegisterList(vixl::aarch32::r10, |