diff options
| author | 2019-07-04 14:02:08 +0100 | |
|---|---|---|
| committer | 2019-07-15 09:18:25 +0000 | |
| commit | 460f05480379d5c75555d06c4938bc990ce6ff83 (patch) | |
| tree | ec76b6d19d7766dc1e57295748122c9352c1397e /compiler/optimizing | |
| parent | dcd7b5188efb9a891ab8511c73e238bcab95432f (diff) | |
ARM: Remove unnecessary kCoreAlwaysSpillRegister.
The old reasoning behind it is invalid as T32 supports
16-bit instructions that can push/pop a single register.
This reduces the frame size of some methods.
Test: m test-art-host-gtest
Test: aosp_taimen-userdebug boots.
Test: run-gtests.sh
Test: testrunner.py --target --optimizing --32
Change-Id: I35955e4394ca262c0b5d2713b2735ed1f5c99c4a
Diffstat (limited to 'compiler/optimizing')
| -rw-r--r-- | compiler/optimizing/code_generator_arm_vixl.cc | 8 | ||||
| -rw-r--r-- | compiler/optimizing/code_generator_arm_vixl.h | 2 |
2 files changed, 4 insertions, 6 deletions
diff --git a/compiler/optimizing/code_generator_arm_vixl.cc b/compiler/optimizing/code_generator_arm_vixl.cc index 99645a4d71..0b7df69d53 100644 --- a/compiler/optimizing/code_generator_arm_vixl.cc +++ b/compiler/optimizing/code_generator_arm_vixl.cc @@ -2061,10 +2061,10 @@ InstructionCodeGeneratorARMVIXL::InstructionCodeGeneratorARMVIXL(HGraph* graph, void CodeGeneratorARMVIXL::ComputeSpillMask() { core_spill_mask_ = allocated_registers_.GetCoreRegisters() & core_callee_save_mask_; - DCHECK_NE(core_spill_mask_, 0u) << "At least the return address register must be saved"; - // There is no easy instruction to restore just the PC on thumb2. We spill and - // restore another arbitrary register. - core_spill_mask_ |= (1 << kCoreAlwaysSpillRegister.GetCode()); + DCHECK_NE(core_spill_mask_ & (1u << kLrCode), 0u) + << "At least the return address register must be saved"; + // 16-bit PUSH/POP (T1) can save/restore just the LR/PC. + DCHECK(GetVIXLAssembler()->IsUsingT32()); fpu_spill_mask_ = allocated_registers_.GetFloatingPointRegisters() & fpu_callee_save_mask_; // We use vpush and vpop for saving and restoring floating point registers, which take // a SRegister and the number of registers to save/restore after that SRegister. We diff --git a/compiler/optimizing/code_generator_arm_vixl.h b/compiler/optimizing/code_generator_arm_vixl.h index 4742f78bae..28dea3db74 100644 --- a/compiler/optimizing/code_generator_arm_vixl.h +++ b/compiler/optimizing/code_generator_arm_vixl.h @@ -76,8 +76,6 @@ static const size_t kParameterFpuRegistersLengthVIXL = arraysize(kParameterFpuRe static const vixl::aarch32::Register kMethodRegister = vixl::aarch32::r0; -static const vixl::aarch32::Register kCoreAlwaysSpillRegister = vixl::aarch32::r5; - // Callee saves core registers r5, r6, r7, r8 (except when emitting Baker // read barriers, where it is used as Marking Register), r10, r11, and lr. static const vixl::aarch32::RegisterList kCoreCalleeSaves = vixl::aarch32::RegisterList::Union( |