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author Mark Mendell <mark.p.mendell@intel.com> 2015-04-09 20:42:42 -0400
committer Mark Mendell <mark.p.mendell@intel.com> 2015-04-10 08:50:40 -0400
commit39dcf55a56da746e04f477f89e7b00ba1de03880 (patch)
tree97bbd68fa538cf76ac26cfeb7a101b5ceb330028 /compiler/optimizing
parentfcfea6324b2913621d5cb642d4315f22c4901368 (diff)
[optimizing] Address x86_64 RIP patch comments
Nicolas had some comments after the patch https://android-review.googlesource.com/#/c/144100 had merged. Fix the problems that he found. Change-Id: I40e8a4273997860db7511dc8f1986281b72bead2 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
Diffstat (limited to 'compiler/optimizing')
-rw-r--r--compiler/optimizing/code_generator_x86_64.cc13
-rw-r--r--compiler/optimizing/code_generator_x86_64.h2
-rw-r--r--compiler/optimizing/intrinsics_x86_64.cc17
3 files changed, 20 insertions, 12 deletions
diff --git a/compiler/optimizing/code_generator_x86_64.cc b/compiler/optimizing/code_generator_x86_64.cc
index c915b0fd83..5710ec57d8 100644
--- a/compiler/optimizing/code_generator_x86_64.cc
+++ b/compiler/optimizing/code_generator_x86_64.cc
@@ -4234,13 +4234,14 @@ void InstructionCodeGeneratorX86_64::VisitBoundType(HBoundType* instruction) {
void CodeGeneratorX86_64::Finalize(CodeAllocator* allocator) {
// Generate the constant area if needed.
- if (!__ IsConstantAreaEmpty()) {
+ X86_64Assembler* assembler = GetAssembler();
+ if (!assembler->IsConstantAreaEmpty()) {
// Align to 4 byte boundary to reduce cache misses, as the data is 4 and 8
// byte values. If used for vectors at a later time, this will need to be
// updated to 16 bytes with the appropriate offset.
- __ Align(4, 0);
- constant_area_start_ = __ CodeSize();
- __ AddConstantArea();
+ assembler->Align(4, 0);
+ constant_area_start_ = assembler->CodeSize();
+ assembler->AddConstantArea();
}
// And finish up.
@@ -4252,7 +4253,7 @@ void CodeGeneratorX86_64::Finalize(CodeAllocator* allocator) {
*/
class RIPFixup : public AssemblerFixup, public ArenaObject<kArenaAllocMisc> {
public:
- RIPFixup(CodeGeneratorX86_64& codegen, int offset)
+ RIPFixup(const CodeGeneratorX86_64& codegen, int offset)
: codegen_(codegen), offset_into_constant_area_(offset) {}
private:
@@ -4266,7 +4267,7 @@ class RIPFixup : public AssemblerFixup, public ArenaObject<kArenaAllocMisc> {
region.StoreUnaligned<int32_t>(pos - 4, relative_position);
}
- CodeGeneratorX86_64& codegen_;
+ const CodeGeneratorX86_64& codegen_;
// Location in constant area that the fixup refers to.
int offset_into_constant_area_;
diff --git a/compiler/optimizing/code_generator_x86_64.h b/compiler/optimizing/code_generator_x86_64.h
index c819eecaf0..aae7de0e42 100644
--- a/compiler/optimizing/code_generator_x86_64.h
+++ b/compiler/optimizing/code_generator_x86_64.h
@@ -297,7 +297,7 @@ class CodeGeneratorX86_64 : public CodeGenerator {
X86_64Assembler assembler_;
const X86_64InstructionSetFeatures& isa_features_;
- // Offset to start of the constant area in the assembled code.
+ // Offset to the start of the constant area in the assembled code.
// Used for fixups to the constant area.
int constant_area_start_;
diff --git a/compiler/optimizing/intrinsics_x86_64.cc b/compiler/optimizing/intrinsics_x86_64.cc
index c0c4ff3388..cbf94f0f81 100644
--- a/compiler/optimizing/intrinsics_x86_64.cc
+++ b/compiler/optimizing/intrinsics_x86_64.cc
@@ -301,15 +301,19 @@ static void CreateFloatToFloatPlusTemps(ArenaAllocator* arena, HInvoke* invoke)
locations->AddTemp(Location::RequiresFpuRegister()); // FP reg to hold mask.
}
-static void MathAbsFP(LocationSummary* locations, bool is64bit,
- X86_64Assembler* assembler, CodeGeneratorX86_64* codegen) {
+static void MathAbsFP(LocationSummary* locations,
+ bool is64bit,
+ X86_64Assembler* assembler,
+ CodeGeneratorX86_64* codegen) {
Location output = locations->Out();
if (output.IsFpuRegister()) {
// In-register
XmmRegister xmm_temp = locations->GetTemp(0).AsFpuRegister<XmmRegister>();
- // TODO: Can mask directly with constant area if we align on 16 bytes.
+ // TODO: Can mask directly with constant area using pand if we can guarantee
+ // that the literal is aligned on a 16 byte boundary. This will avoid a
+ // temporary.
if (is64bit) {
__ movsd(xmm_temp, codegen->LiteralInt64Address(INT64_C(0x7FFFFFFFFFFFFFFF)));
__ andpd(output.AsFpuRegister<XmmRegister>(), xmm_temp);
@@ -397,8 +401,11 @@ void IntrinsicCodeGeneratorX86_64::VisitMathAbsLong(HInvoke* invoke) {
GenAbsInteger(invoke->GetLocations(), true, GetAssembler());
}
-static void GenMinMaxFP(LocationSummary* locations, bool is_min, bool is_double,
- X86_64Assembler* assembler, CodeGeneratorX86_64* codegen) {
+static void GenMinMaxFP(LocationSummary* locations,
+ bool is_min,
+ bool is_double,
+ X86_64Assembler* assembler,
+ CodeGeneratorX86_64* codegen) {
Location op1_loc = locations->InAt(0);
Location op2_loc = locations->InAt(1);
Location out_loc = locations->Out();