diff options
| author | 2017-11-08 19:59:32 +0000 | |
|---|---|---|
| committer | 2017-11-08 19:59:32 +0000 | |
| commit | 16c1f723f1bc0d02e757a6cf2133882dbcb9600e (patch) | |
| tree | d0d2293f35079e498a086d9318859abc5198076c /compiler/optimizing | |
| parent | b630031786e96d4246697fdc15e1934047b0916b (diff) | |
| parent | 7a0222e78ca39dc8f8e084b0c84f71a10852d24a (diff) | |
Merge "MIPS32: Don't leave vector registers in an unpredictable state"
Diffstat (limited to 'compiler/optimizing')
| -rw-r--r-- | compiler/optimizing/code_generator_vector_mips.cc | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/compiler/optimizing/code_generator_vector_mips.cc b/compiler/optimizing/code_generator_vector_mips.cc index 7a8c0ad025..384b642145 100644 --- a/compiler/optimizing/code_generator_vector_mips.cc +++ b/compiler/optimizing/code_generator_vector_mips.cc @@ -68,8 +68,12 @@ void InstructionCodeGeneratorMIPS::VisitVecReplicateScalar(HVecReplicateScalar* break; case DataType::Type::kInt64: DCHECK_EQ(2u, instruction->GetVectorLength()); - __ Mtc1(locations->InAt(0).AsRegisterPairLow<Register>(), FTMP); - __ MoveToFpuHigh(locations->InAt(0).AsRegisterPairHigh<Register>(), FTMP); + __ InsertW(static_cast<VectorRegister>(FTMP), + locations->InAt(0).AsRegisterPairLow<Register>(), + 0); + __ InsertW(static_cast<VectorRegister>(FTMP), + locations->InAt(0).AsRegisterPairHigh<Register>(), + 1); __ ReplicateFPToVectorRegister(dst, FTMP, /* is_double */ true); break; case DataType::Type::kFloat32: @@ -124,10 +128,8 @@ void InstructionCodeGeneratorMIPS::VisitVecExtractScalar(HVecExtractScalar* inst break; case DataType::Type::kInt64: DCHECK_EQ(2u, instruction->GetVectorLength()); - __ Mfc1(locations->Out().AsRegisterPairLow<Register>(), - locations->InAt(0).AsFpuRegister<FRegister>()); - __ MoveFromFpuHigh(locations->Out().AsRegisterPairHigh<Register>(), - locations->InAt(0).AsFpuRegister<FRegister>()); + __ Copy_sW(locations->Out().AsRegisterPairLow<Register>(), src, 0); + __ Copy_sW(locations->Out().AsRegisterPairHigh<Register>(), src, 1); break; case DataType::Type::kFloat32: case DataType::Type::kFloat64: @@ -987,10 +989,8 @@ void InstructionCodeGeneratorMIPS::VisitVecSetScalars(HVecSetScalars* instructio break; case DataType::Type::kInt64: DCHECK_EQ(2u, instruction->GetVectorLength()); - __ Mtc1(locations->InAt(0).AsRegisterPairLow<Register>(), - locations->Out().AsFpuRegister<FRegister>()); - __ MoveToFpuHigh(locations->InAt(0).AsRegisterPairHigh<Register>(), - locations->Out().AsFpuRegister<FRegister>()); + __ InsertW(dst, locations->InAt(0).AsRegisterPairLow<Register>(), 0); + __ InsertW(dst, locations->InAt(0).AsRegisterPairHigh<Register>(), 1); break; default: LOG(FATAL) << "Unsupported SIMD type"; |