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| author | 2023-09-21 12:02:35 -0700 | |
|---|---|---|
| committer | 2023-09-27 00:26:16 -0700 | |
| commit | 1be0dba41d334d3f5c0355922ca1bc60ecdb39d5 (patch) | |
| tree | 85bc208e0480f461e2b233e01420376b6d5a550d /compiler/optimizing/stack_map_test.cc | |
| parent | 4646fc66fc85b97a03eb76819bb367181a306ca2 (diff) | |
riscv64: store double result in two vreg slots
Test: Run these opcodes against all interpreter
tests on a Linux RISC-V VM.
(1) setup
lunch aosp_riscv64-userdebug
export ART_TEST_SSH_USER=ubuntu
export ART_TEST_SSH_HOST=localhost
export ART_TEST_SSH_PORT=10001
export ART_TEST_ON_VM=true
. art/tools/buildbot-utils.sh
art/tools/buildbot-build.sh --target
# Create, boot and configure the VM.
art/tools/buildbot-vm.sh create
art/tools/buildbot-vm.sh boot
art/tools/buildbot-vm.sh setup-ssh # password: 'ubuntu'
art/tools/buildbot-cleanup-device.sh
art/tools/buildbot-setup-device.sh
art/tools/buildbot-sync.sh
(2) test
art/test.py --target -r --no-prebuild --ndebug --64 -j 12 --cdex-none --interpreter
Clean with `m check_cfi` too.
Also exercised on cuttlefish boot. No SIGSEGV or SIGILL noted.
Bug: 283082047
Change-Id: I6317bd21236c569e32aba7bd300ecc78d1831e3b
Diffstat (limited to 'compiler/optimizing/stack_map_test.cc')
0 files changed, 0 insertions, 0 deletions