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author Santiago Aboy Solanes <solanes@google.com> 2024-01-25 09:56:06 +0000
committer Santiago Aboy Solanes <solanes@google.com> 2024-01-29 08:47:22 +0000
commitd76551c7229060a3fe11258b490a11f4ee91e9f8 (patch)
treef8fcb5e839b1d2c0a61347b764f6a76dda117a84 /compiler/optimizing/scheduler_arm.cc
parentb782659336403e125e33f829afad49b901027c22 (diff)
Revert^7 "Disable write-barrier elimination pass"
This reverts commit 1ba3516e8c3e2b86c73084893dd297f468469181. Reason for revert: PS1 is reland as-is PS2 has two related fixes (for RISC-V and arm64) taking into account that when we store zero, we use a special register. Bug: 301833859 Bug: 310755375 Bug: 260843353 Test: lunch cf_riscv64_wear-trunk_staging-userdebug && m Test: lunch starnix_wear_yukawa-trunk_staging-userdebug && m Change-Id: I5e69890fd56404ddde56ebc457179241363d9243
Diffstat (limited to 'compiler/optimizing/scheduler_arm.cc')
-rw-r--r--compiler/optimizing/scheduler_arm.cc4
1 files changed, 1 insertions, 3 deletions
diff --git a/compiler/optimizing/scheduler_arm.cc b/compiler/optimizing/scheduler_arm.cc
index cafb0f5da6..510a0f5496 100644
--- a/compiler/optimizing/scheduler_arm.cc
+++ b/compiler/optimizing/scheduler_arm.cc
@@ -977,8 +977,6 @@ void SchedulingLatencyVisitorARM::HandleFieldSetLatencies(HInstruction* instruct
DCHECK(codegen_ != nullptr);
bool is_volatile = field_info.IsVolatile();
DataType::Type field_type = field_info.GetFieldType();
- bool needs_write_barrier =
- CodeGenerator::StoreNeedsWriteBarrier(field_type, instruction->InputAt(1));
bool atomic_ldrd_strd = codegen_->GetInstructionSetFeatures().HasAtomicLdrdAndStrd();
switch (field_type) {
@@ -997,7 +995,7 @@ void SchedulingLatencyVisitorARM::HandleFieldSetLatencies(HInstruction* instruct
case DataType::Type::kInt32:
case DataType::Type::kReference:
- if (kPoisonHeapReferences && needs_write_barrier) {
+ if (kPoisonHeapReferences && field_type == DataType::Type::kReference) {
last_visited_internal_latency_ += kArmIntegerOpLatency * 2;
}
last_visited_latency_ = kArmMemoryStoreLatency;