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author | 2024-01-24 17:42:08 +0000 | |
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committer | 2024-01-24 22:21:16 +0000 | |
commit | 1ba3516e8c3e2b86c73084893dd297f468469181 (patch) | |
tree | 4b0c99a53fff26f6fe9489049f1830c54af08b86 /compiler/optimizing/scheduler_arm.cc | |
parent | 6b866347f77e264143cf3fbc677c3da0ef9acd5b (diff) |
Revert^6 "Disable write-barrier elimination pass"
This reverts commit 1be176f5a78750e2f0e32470f8c83e3d1643954d.
Reason for revert: Potential cause of build breakage for cf_riscv64_wear-trunk_staging-userdebug build 11353124
Change-Id: I5db1c9fba1edd4ab1eef30e2b547bb9649af5c10
Diffstat (limited to 'compiler/optimizing/scheduler_arm.cc')
-rw-r--r-- | compiler/optimizing/scheduler_arm.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/compiler/optimizing/scheduler_arm.cc b/compiler/optimizing/scheduler_arm.cc index 510a0f5496..cafb0f5da6 100644 --- a/compiler/optimizing/scheduler_arm.cc +++ b/compiler/optimizing/scheduler_arm.cc @@ -977,6 +977,8 @@ void SchedulingLatencyVisitorARM::HandleFieldSetLatencies(HInstruction* instruct DCHECK(codegen_ != nullptr); bool is_volatile = field_info.IsVolatile(); DataType::Type field_type = field_info.GetFieldType(); + bool needs_write_barrier = + CodeGenerator::StoreNeedsWriteBarrier(field_type, instruction->InputAt(1)); bool atomic_ldrd_strd = codegen_->GetInstructionSetFeatures().HasAtomicLdrdAndStrd(); switch (field_type) { @@ -995,7 +997,7 @@ void SchedulingLatencyVisitorARM::HandleFieldSetLatencies(HInstruction* instruct case DataType::Type::kInt32: case DataType::Type::kReference: - if (kPoisonHeapReferences && field_type == DataType::Type::kReference) { + if (kPoisonHeapReferences && needs_write_barrier) { last_visited_internal_latency_ += kArmIntegerOpLatency * 2; } last_visited_latency_ = kArmMemoryStoreLatency; |