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author Roman Artemev <roman.artemev@syntacore.com> 2024-03-21 17:11:10 +0300
committer Treehugger Robot <android-test-infra-autosubmit@system.gserviceaccount.com> 2024-03-25 13:45:19 +0000
commitebb73e09b96a442f5e8100a1ff4cf43815aa441e (patch)
tree3174121d7a498797547d5c393cd9c97dad41681d /compiler/optimizing/optimizing_unit_test.h
parent56dcaeec46dd53e271d6f201d2028996bf19f9dd (diff)
riscv64: Add comment into Riscv64Assembler::Add
In case of 'add rd, Zero, Zero' we could use conversion into 'c.li rd, 0' but for some reason clang does not support it so it could not be tested. Test: None Bug: 328561342 Change-Id: I6efab426bf72330e3df2d6122bc83a3499ac4c9e
Diffstat (limited to 'compiler/optimizing/optimizing_unit_test.h')
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