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author Artem Serov <artem.serov@linaro.org> 2017-04-27 16:50:47 +0100
committer Artem Serov <artem.serov@linaro.org> 2017-05-11 10:06:04 +0100
commite1811ed6b57a54dc8ebd327e4bd2c4422092a3a0 (patch)
treee3ce48e66190c11a8b5342f4ec0d1046ba28d788 /compiler/optimizing/nodes_vector.h
parent7113885fcd983b33ee1e350865d21517d6297843 (diff)
ARM64: Share address computation across SIMD LDRs/STRs.
For array accesses the element address has the following structure: Address = CONST_OFFSET + base_addr + index << ELEM_SHIFT Taking into account ARM64 LDR/STR addressing modes address part (CONST_OFFSET + index << ELEM_SHIFT) can be shared across array access with the same data type and index. For example, for the following loop 5 accesses can share address computation: void foo(int[] a, int[] b, int[] c) { for (i...) { a[i] = a[i] + 5; b[i] = b[i] + c[i]; } } Test: test-art-host, test-art-target Change-Id: I46af3b4e4a55004336672cdba3296b7622d815ca
Diffstat (limited to 'compiler/optimizing/nodes_vector.h')
-rw-r--r--compiler/optimizing/nodes_vector.h7
1 files changed, 6 insertions, 1 deletions
diff --git a/compiler/optimizing/nodes_vector.h b/compiler/optimizing/nodes_vector.h
index 52c247b52f..92fe9bfa7d 100644
--- a/compiler/optimizing/nodes_vector.h
+++ b/compiler/optimizing/nodes_vector.h
@@ -178,12 +178,17 @@ class HVecMemoryOperation : public HVecOperation {
size_t vector_length,
uint32_t dex_pc)
: HVecOperation(arena, packed_type, side_effects, number_of_inputs, vector_length, dex_pc),
- alignment_(Primitive::ComponentSize(packed_type), 0) { }
+ alignment_(Primitive::ComponentSize(packed_type), 0) {
+ DCHECK_GE(number_of_inputs, 2u);
+ }
void SetAlignment(Alignment alignment) { alignment_ = alignment; }
Alignment GetAlignment() const { return alignment_; }
+ HInstruction* GetArray() const { return InputAt(0); }
+ HInstruction* GetIndex() const { return InputAt(1); }
+
DECLARE_ABSTRACT_INSTRUCTION(VecMemoryOperation);
private: