Don't use predicated vectorization by default.

This patch sets the traditional vectorization mode to be
the default one; previously, if the target supported
predicated vectorization (e.g. arm64 SVE), predicated
vectorization was be tried for ALL loops.

Motivation: this is a prerequisite for the further patches
to enable mixed mode vectorization - when most of the loops
are vectorized in traditional mode and some others - in
predicated.

A new env variable - ART_FORCE_TRY_PREDICATED_SIMD - is
introduced to force-use the predicated mode; this could be
set to true for testing purposes.

Checker tests are adjusted accordingly - to also check the
ART_FORCE_TRY_PREDICATED_SIMD variable.

Test: test-art-target, test-art-host.
Test: test-art-target with ART_FORCE_TRY_PREDICATED_SIMD=true.

Original author: Artem Serov <Artem.Serov@linaro.org>

Test: ./art/test/testrunner/testrunner.py --host --optimizing --jit
Test: ./art/test/testrunner/testrunner.py --target --optimizing --jit
      (with ART_FORCE_TRY_PREDICATED_SIMD=true and without)

Test: 661-checker-simd-cf-loops.
Test: target tests on arm64 with SVE
Change-Id: I57852f3777da6f86d615429d1a3c703cb87fbac8

0 files changed, 0 insertions, 0 deletions