diff options
| author | 2017-07-14 14:34:22 +0100 | |
|---|---|---|
| committer | 2017-07-14 17:25:39 +0100 | |
| commit | 9983e302384c12a975c8d2d5ae239f79fd8e1996 (patch) | |
| tree | 4e4d269fe1a3d4f0f1b93cd972adab9f17aab8e0 /compiler/optimizing/intrinsics_arm_vixl.cc | |
| parent | bac2bd1c2fbdd94f4d4dfe83d8451f655e875e36 (diff) | |
Remove the old ARM code generator from ART's Optimizing compiler.
The AArch32 VIXL-based code generator has been the default
ARM code generator in ART for some time now. The old ARM
code generator does not compile anymore; retiring it.
Test: test.py
Bug: 63316036
Change-Id: Iab8fbc4ac73eac2c1a809cd7b22fec6b619755db
Diffstat (limited to 'compiler/optimizing/intrinsics_arm_vixl.cc')
| -rw-r--r-- | compiler/optimizing/intrinsics_arm_vixl.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/compiler/optimizing/intrinsics_arm_vixl.cc b/compiler/optimizing/intrinsics_arm_vixl.cc index ced931b36b..8b4044d69b 100644 --- a/compiler/optimizing/intrinsics_arm_vixl.cc +++ b/compiler/optimizing/intrinsics_arm_vixl.cc @@ -1058,7 +1058,7 @@ static void CreateIntIntIntToIntLocations(ArenaAllocator* arena, (can_call ? Location::kOutputOverlap : Location::kNoOutputOverlap)); if (type == Primitive::kPrimNot && kEmitCompilerReadBarrier && kUseBakerReadBarrier) { // We need a temporary register for the read barrier marking slow - // path in InstructionCodeGeneratorARM::GenerateReferenceLoadWithBakerReadBarrier. + // path in CodeGeneratorARMVIXL::GenerateReferenceLoadWithBakerReadBarrier. locations->AddTemp(Location::RequiresRegister()); } } @@ -2377,7 +2377,7 @@ void IntrinsicCodeGeneratorARMVIXL::VisitSystemArrayCopy(HInvoke* invoke) { // TODO: Also convert this intrinsic to the IsGcMarking strategy? // SystemArrayCopy implementation for Baker read barriers (see - // also CodeGeneratorARM::GenerateReferenceLoadWithBakerReadBarrier): + // also CodeGeneratorARMVIXL::GenerateReferenceLoadWithBakerReadBarrier): // // uint32_t rb_state = Lockword(src->monitor_).ReadBarrierState(); // lfence; // Load fence or artificial data dependency to prevent load-load reordering |