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| author | 2016-01-12 12:01:04 +0000 | |
|---|---|---|
| committer | 2016-01-12 12:01:04 +0000 | |
| commit | 4bedb3845ac33c95cb779987abd4e76a88b19989 (patch) | |
| tree | d8de13e932035710f32acdf9340970bc1eb89a90 /compiler/optimizing/intrinsics_arm.cc | |
| parent | 363910e676f388b87478e553c243157d395ffc3c (diff) | |
Fix memory fences in the ARM64 UnsafeCas intrinsics.
Also add some comments for the ARM UnsafeCas intrinsics.
Change-Id: Ic6e4f2c37e468db4582ac8709496a80f3c1f9a6b
Diffstat (limited to 'compiler/optimizing/intrinsics_arm.cc')
| -rw-r--r-- | compiler/optimizing/intrinsics_arm.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/compiler/optimizing/intrinsics_arm.cc b/compiler/optimizing/intrinsics_arm.cc index 1e6b3a1fb3..b1fbf28204 100644 --- a/compiler/optimizing/intrinsics_arm.cc +++ b/compiler/optimizing/intrinsics_arm.cc @@ -847,6 +847,9 @@ static void GenCas(LocationSummary* locations, Primitive::Type type, CodeGenerat } // Prevent reordering with prior memory operations. + // Emit a DMB ISH instruction instead of an DMB ISHST one, as the + // latter allows a preceding load to be delayed past the STXR + // instruction below. __ dmb(ISH); __ add(tmp_ptr, base, ShifterOperand(offset)); |