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| author | 2024-05-30 17:05:54 +0500 | |
|---|---|---|
| committer | 2024-06-12 10:42:45 +0000 | |
| commit | b658a268e2e76e429702c2929d24ebbbf909e947 (patch) | |
| tree | 2366f34aecd290dcc988dbb3d1923e9471d8370e /compiler/optimizing/instruction_simplifier_shared.h | |
| parent | 05e428dacb0b4877960e3b1c0d50cb9c90f378d5 (diff) | |
riscv: Expand BitwiseNegatedRight to riscv64, optimize
Add BitwiseNegatedRight optimization for riscv:
And + Not -> AndNot
Or + Not -> OrNot
Xor + Not -> XorNot
By compiling facebook app using dex2oat I got:
169 cases of And + Not pattern
9 cases of Or + Not pattern
1 case of Xor + Not pattern.
Test: art/test/testrunner/testrunner.py --target --64 --ndebug --optimizing
Change-Id: Icc2db96770378005d2fb01176298a067e1a0e4ad
Diffstat (limited to 'compiler/optimizing/instruction_simplifier_shared.h')
| -rw-r--r-- | compiler/optimizing/instruction_simplifier_shared.h | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/compiler/optimizing/instruction_simplifier_shared.h b/compiler/optimizing/instruction_simplifier_shared.h index ca6d5286c5..de70ec5a8a 100644 --- a/compiler/optimizing/instruction_simplifier_shared.h +++ b/compiler/optimizing/instruction_simplifier_shared.h @@ -62,18 +62,6 @@ inline bool IsSubRightSubLeftShl(HSub *sub) { } // namespace helpers bool TryCombineMultiplyAccumulate(HMul* mul, InstructionSet isa); -// For bitwise operations (And/Or/Xor) with a negated input, try to use -// a negated bitwise instruction. -bool TryMergeNegatedInput(HBinaryOperation* op); - -// Convert -// i1: AND a, b -// SUB a, i1 -// into: -// BIC a, a, b -// -// It also works if `i1` is AND b, a -bool TryMergeWithAnd(HSub* instruction); bool TryExtractArrayAccessAddress(CodeGenerator* codegen, HInstruction* access, |