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| author | 2024-02-29 16:09:29 +0000 | |
|---|---|---|
| committer | 2024-03-06 08:22:54 +0000 | |
| commit | 04a110dadb8088eaac2c5ac014327c6335c2b8dd (patch) | |
| tree | 0c8b8cdea2f7bdfe922fb7dc9bd979fb612cdea7 /compiler/optimizing/instruction_simplifier_shared.h | |
| parent | 9fa9678fa177ff480a1e5e509757d498bf7bf555 (diff) | |
Convert And+Sub into bic if possible
Convert
i1: AND a, b
SUB a, i1
into:
BIC a, a, b
Also works if `i1` is AND b, a.
Bug: 304972513
Fixes: 304972513
Test: art/test/testrunner/testrunner.py --host --64 --target
Change-Id: I22218c263f52b58d87431186588ac166dc93246a
Diffstat (limited to 'compiler/optimizing/instruction_simplifier_shared.h')
| -rw-r--r-- | compiler/optimizing/instruction_simplifier_shared.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/compiler/optimizing/instruction_simplifier_shared.h b/compiler/optimizing/instruction_simplifier_shared.h index 68148cff7e..ca6d5286c5 100644 --- a/compiler/optimizing/instruction_simplifier_shared.h +++ b/compiler/optimizing/instruction_simplifier_shared.h @@ -66,6 +66,15 @@ bool TryCombineMultiplyAccumulate(HMul* mul, InstructionSet isa); // a negated bitwise instruction. bool TryMergeNegatedInput(HBinaryOperation* op); +// Convert +// i1: AND a, b +// SUB a, i1 +// into: +// BIC a, a, b +// +// It also works if `i1` is AND b, a +bool TryMergeWithAnd(HSub* instruction); + bool TryExtractArrayAccessAddress(CodeGenerator* codegen, HInstruction* access, HInstruction* array, |