riscv: Expand BitwiseNegatedRight to riscv64, optimize

Add BitwiseNegatedRight optimization for riscv:
And + Not -> AndNot
Or  + Not -> OrNot
Xor + Not -> XorNot

By compiling facebook app using dex2oat I got:
169 cases of And + Not pattern
9 cases of    Or + Not pattern
1 case of    Xor + Not pattern.

Test: art/test/testrunner/testrunner.py --target --64 --ndebug --optimizing

Change-Id: Icc2db96770378005d2fb01176298a067e1a0e4ad

1 files changed, 13 insertions, 0 deletions

diff --git a/compiler/optimizing/instruction_simplifier.h b/compiler/optimizing/instruction_simplifier.h
index 98ebaafebc..6f9e1f334e 100644
--- a/compiler/optimizing/instruction_simplifier.h
+++ b/compiler/optimizing/instruction_simplifier.h
@@ -60,6 +60,19 @@ class InstructionSimplifier : public HOptimization {
   DISALLOW_COPY_AND_ASSIGN(InstructionSimplifier);
 };
 
+// For bitwise operations (And/Or/Xor) with a negated input, try to use
+// a negated bitwise instruction.
+bool TryMergeNegatedInput(HBinaryOperation* op);
+
+// Convert
+// i1: AND a, b
+//     SUB a, i1
+// into:
+//     BIC a, a, b
+//
+// It also works if `i1` is AND b, a
+bool TryMergeWithAnd(HSub* instruction);
+
 }  // namespace art
 
 #endif  // ART_COMPILER_OPTIMIZING_INSTRUCTION_SIMPLIFIER_H_