riscv64: add float NaN-boxing in `BuildNativeCallFrameStateMachine`.

RISC-V manual, the D extension chapter, explains NaN boxing:

  When multiple floating-point precisions are supported, valid values of
  narrower n-bit types, n < FLEN, are represented in the lower n bits of
  an FLEN-bit NaN value, in a process termed NaN-boxing. The upper bits
  of a valid NaN-boxed value must be all 1s. Valid NaN-boxed n-bit
  values therefore appear as negative quiet NaNs (qNaNs) when viewed as
  any wider m-bit value, n < m <= FLEN. Any operation that writes a
  narrower result to an f register must write all 1s to the uppermost
  FLEN−n bits to yield a legal NaN-boxed value.

Test: lunch aosp_riscv64-userdebug \
  && art/tools/buildbot-build.sh --target
Change-Id: If75a7ad277f56909d512cb681e775135c1420d4d

0 files changed, 0 insertions, 0 deletions