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| author | 2023-01-25 11:57:09 +0000 | |
|---|---|---|
| committer | 2023-02-09 09:56:04 +0000 | |
| commit | e2c7f90282c0deb39b7060959308e9daa1aa739e (patch) | |
| tree | c110f8cae79606f3b30b597f6d016cc132138813 /compiler/optimizing/find_loops_test.cc | |
| parent | 8ce90803c958023fd8e5009fe682c821ed020d53 (diff) | |
riscv64: define callee-saved frame layout.
Define which registers are saved/restored by different types of ART
callee-saved frames. This is based on the standard RISC-V calling
convention (https://github.com/riscv-non-isa/riscv-elf-psabi-doc) and
also ART internal convention (Quick ABI) that defines additional
ART-specific meaning of some registers (e.g. the ART thread register).
Test: lunch aosp_riscv64-userdebug && m dist
Co-authored-by: Ulya Trafimovich <skvadrik@google.com>
Change-Id: Ifd2fafcb94e7fac9da6bf41544c47d576bcc9560
Diffstat (limited to 'compiler/optimizing/find_loops_test.cc')
0 files changed, 0 insertions, 0 deletions