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| author | 2014-11-06 17:31:04 +0000 | |
|---|---|---|
| committer | 2014-11-06 17:31:04 +0000 | |
| commit | 7f4ffd2d9309b93ab8b58734be501d6fa18460d4 (patch) | |
| tree | fc86926faf45766d5fa93fd20a2e216ae017ff8b /compiler/optimizing/codegen_test.cc | |
| parent | df3b41f993d6c13ba318333ef4cdf718ecf5a4d1 (diff) | |
| parent | 9b6c62b82e3d40d70d541920d5f7f81ad517bc01 (diff) | |
am 9b6c62b8: Merge "[optimizing compiler] Add DIV_INT_2ADDR"
* commit '9b6c62b82e3d40d70d541920d5f7f81ad517bc01':
[optimizing compiler] Add DIV_INT_2ADDR
Diffstat (limited to 'compiler/optimizing/codegen_test.cc')
| -rw-r--r-- | compiler/optimizing/codegen_test.cc | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/compiler/optimizing/codegen_test.cc b/compiler/optimizing/codegen_test.cc index a7b64c9e3b..ecee44392e 100644 --- a/compiler/optimizing/codegen_test.cc +++ b/compiler/optimizing/codegen_test.cc @@ -625,4 +625,18 @@ TEST(CodegenTest, ReturnDivIntLit8) { TestCode(data, true, 1); } +#if defined(__aarch64__) +TEST(CodegenTest, DISABLED_ReturnDivInt2Addr) { +#else +TEST(CodegenTest, ReturnDivInt2Addr) { +#endif + const uint16_t data[] = TWO_REGISTERS_CODE_ITEM( + Instruction::CONST_4 | 4 << 12 | 0, + Instruction::CONST_4 | 2 << 12 | 1 << 8, + Instruction::DIV_INT_2ADDR | 1 << 12, + Instruction::RETURN); + + TestCode(data, true, 2); +} + } // namespace art |