diff options
| author | 2023-06-16 12:18:27 +0100 | |
|---|---|---|
| committer | 2023-06-21 07:59:13 +0000 | |
| commit | 70bba9c9f5fbba03c62a4542411e1d938375f14e (patch) | |
| tree | 0b4ef702e671db908321639d39912636603166bc /compiler/optimizing/codegen_test.cc | |
| parent | 5bf0f68407d3467a3fbfa9ab9ae0c8fabead615b (diff) | |
Remove CodeAllocator and the extra copy of generated code.
The code used to copy the final generated code twice: from assembler to
CodeAllocator, and then to CodeAllocator to SwapAllocator/JitMemory.
The assemblers never depended on the exact location of the generated
code, so just drop that feature.
Test: test.py
Change-Id: I8dc82e4926097092b9aac336a5a5d40f79dc62ca
Diffstat (limited to 'compiler/optimizing/codegen_test.cc')
| -rw-r--r-- | compiler/optimizing/codegen_test.cc | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/compiler/optimizing/codegen_test.cc b/compiler/optimizing/codegen_test.cc index 2d9acc49b3..f890ba9cc0 100644 --- a/compiler/optimizing/codegen_test.cc +++ b/compiler/optimizing/codegen_test.cc @@ -733,8 +733,7 @@ TEST_F(CodegenTest, ARMVIXLParallelMoveResolver) { move->AddMove(Location::StackSlot(8192), Location::StackSlot(0), DataType::Type::kInt32, nullptr); codegen.GetMoveResolver()->EmitNativeCode(move); - InternalCodeAllocator code_allocator; - codegen.Finalize(&code_allocator); + codegen.Finalize(); } #endif @@ -785,8 +784,7 @@ TEST_F(CodegenTest, ARM64ParallelMoveResolverB34760542) { nullptr); codegen.GetMoveResolver()->EmitNativeCode(move); - InternalCodeAllocator code_allocator; - codegen.Finalize(&code_allocator); + codegen.Finalize(); } // Check that ParallelMoveResolver works fine for ARM64 for both cases when SIMD is on and off. @@ -821,8 +819,7 @@ TEST_F(CodegenTest, ARM64ParallelMoveResolverSIMD) { graph->SetHasSIMD(false); } - InternalCodeAllocator code_allocator; - codegen.Finalize(&code_allocator); + codegen.Finalize(); } // Check that ART ISA Features are propagated to VIXL for arm64 (using cortex-a75 as example). |