diff options
| author | 2021-12-14 23:16:21 +0000 | |
|---|---|---|
| committer | 2023-07-12 11:02:57 +0000 | |
| commit | 0b284aaa0f2b7c89591ac494e71af40adc8cf15d (patch) | |
| tree | ba38e4ad5152bfaeeeb26e4185b7614c7f23e229 /compiler/optimizing/codegen_test.cc | |
| parent | 3bf7e912091f266a01c5a4fe09b082bea1c383f2 (diff) | |
Support autovectorization of diamond loops.
This CL enables predicated autovectorization of loops with
control flow, currently only for simple diamond pattern ones:
header------------------+
| |
diamond_hif |
/ \ |
diamond_true diamond_false |
\ / |
back_edge |
| |
+---------------------+
Original author: Artem Serov <Artem.Serov@linaro.org>
Test: ./art/test.py --host --optimizing --jit
Test: ./art/test.py --target --optimizing --jit
Test: 661-checker-simd-cf-loops.
Test: target tests on arm64 with SVE (for details see
art/test/README.arm_fvp).
Change-Id: I8dbc266278b4ab074b831d6c224f02024030cc8a
Diffstat (limited to 'compiler/optimizing/codegen_test.cc')
| -rw-r--r-- | compiler/optimizing/codegen_test.cc | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/compiler/optimizing/codegen_test.cc b/compiler/optimizing/codegen_test.cc index f890ba9cc0..c72d3ea24a 100644 --- a/compiler/optimizing/codegen_test.cc +++ b/compiler/optimizing/codegen_test.cc @@ -796,7 +796,7 @@ TEST_F(CodegenTest, ARM64ParallelMoveResolverSIMD) { codegen.Initialize(); - graph->SetHasSIMD(true); + graph->SetHasTraditionalSIMD(true); for (int i = 0; i < 2; i++) { HParallelMove* move = new (graph->GetAllocator()) HParallelMove(graph->GetAllocator()); move->AddMove(Location::SIMDStackSlot(0), @@ -816,7 +816,7 @@ TEST_F(CodegenTest, ARM64ParallelMoveResolverSIMD) { DataType::Type::kFloat64, nullptr); codegen.GetMoveResolver()->EmitNativeCode(move); - graph->SetHasSIMD(false); + graph->SetHasTraditionalSIMD(false); } codegen.Finalize(); @@ -864,7 +864,7 @@ TEST_F(CodegenTest, ARM64FrameSizeSIMD) { arm64::CodeGeneratorARM64 codegen(graph, *compiler_options); codegen.Initialize(); - graph->SetHasSIMD(true); + graph->SetHasTraditionalSIMD(true); DCHECK_EQ(arm64::callee_saved_fp_registers.GetCount(), 8); vixl::aarch64::CPURegList reg_list = arm64::callee_saved_fp_registers; @@ -884,7 +884,8 @@ TEST_F(CodegenTest, ARM64FrameSizeNoSIMD) { arm64::CodeGeneratorARM64 codegen(graph, *compiler_options); codegen.Initialize(); - graph->SetHasSIMD(false); + graph->SetHasTraditionalSIMD(false); + graph->SetHasPredicatedSIMD(false); DCHECK_EQ(arm64::callee_saved_fp_registers.GetCount(), 8); vixl::aarch64::CPURegList reg_list = arm64::callee_saved_fp_registers; |