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author Nicolas Geoffray <ngeoffray@google.com> 2015-01-07 16:01:24 +0000
committer Nicolas Geoffray <ngeoffray@google.com> 2015-01-08 13:57:51 +0000
commit840e5461a85f8908f51e7f6cd562a9129ff0e7ce (patch)
treeea8b4cbc5a0e3dea96fefcd9247e6c06b17ac518 /compiler/optimizing/code_generator.cc
parent893e8881e31180721512c1b9e5ffacb03aad2e45 (diff)
Implement double and float support for arm in register allocator.
The basic approach is: - An instruction that needs two registers gets two intervals. - When allocating the low part, we also allocate the high part. - When splitting a low (or high) interval, we also split the high (or low) equivalent. - Allocation follows the (S/D register) requirement that low registers are always even and the high equivalent is low + 1. Change-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797
Diffstat (limited to 'compiler/optimizing/code_generator.cc')
-rw-r--r--compiler/optimizing/code_generator.cc8
1 files changed, 8 insertions, 0 deletions
diff --git a/compiler/optimizing/code_generator.cc b/compiler/optimizing/code_generator.cc
index 4d8154e6a0..ada0fb75d7 100644
--- a/compiler/optimizing/code_generator.cc
+++ b/compiler/optimizing/code_generator.cc
@@ -620,6 +620,14 @@ void CodeGenerator::RecordPcInfo(HInstruction* instruction, uint32_t dex_pc) {
break;
}
+ case Location::kFpuRegisterPair : {
+ stack_map_stream_.AddDexRegisterEntry(DexRegisterMap::kInFpuRegister, location.low());
+ stack_map_stream_.AddDexRegisterEntry(DexRegisterMap::kInFpuRegister, location.high());
+ ++i;
+ DCHECK_LT(i, environment_size);
+ break;
+ }
+
default:
LOG(FATAL) << "Unexpected kind " << location.GetKind();
}