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| author | 2020-09-30 08:33:10 +0000 | |
|---|---|---|
| committer | 2021-09-06 08:58:50 +0000 | |
| commit | 0700b69cb0c81c3590726be7fbe5b98531cec76b (patch) | |
| tree | 9699ae3c78a2c7546918ba03aa43b0306d4f48a5 /compiler/optimizing/code_generator.cc | |
| parent | 6194403a984dd814f01e6f7c6b270342d760388d (diff) | |
SVE: Extract Intermediate Address for SVE Vector Memory Operations
This patch introduces an optimization that extracts and factorizes
the "base + offset" common part for the address computation when
performing an SVE vector memory operation (VecStore/VecLoad).
With SVE enabled by default:
Test: ./art/test.py --simulate-arm64 --run-test --optimizing \
(With the VIXL simulator patch)
Test: ./art/test.py --target --64 --optimizing \
(On Arm FVP with SVE - See steps in test/README.arm_fvp.md)
Test: 527-checker-array-access, 655-checker-simd-arm.
Change-Id: Icd49e57d5550d1530445a94e5d49e217a999d06d
Diffstat (limited to 'compiler/optimizing/code_generator.cc')
0 files changed, 0 insertions, 0 deletions