diff options
| author | 2014-06-24 18:44:29 +0000 | |
|---|---|---|
| committer | 2014-06-24 18:00:13 +0000 | |
| commit | fbd18f1923334f3208cfe6ba5f1d4f9eb421b063 (patch) | |
| tree | 79eefb2dd1ae2cade357ef5d8367973bd08b0a34 /compiler/dex/quick/ralloc_util.cc | |
| parent | 7e47f713067b55e24b5d24f2c892ceefd7971ebf (diff) | |
| parent | de68676b24f61a55adc0b22fe828f036a5925c41 (diff) | |
Merge "Revert "ART: Split out more cases of Load/StoreRef, volatile as parameter""
Diffstat (limited to 'compiler/dex/quick/ralloc_util.cc')
| -rw-r--r-- | compiler/dex/quick/ralloc_util.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/compiler/dex/quick/ralloc_util.cc b/compiler/dex/quick/ralloc_util.cc index 60eebe4a25..5bb0ee04d4 100644 --- a/compiler/dex/quick/ralloc_util.cc +++ b/compiler/dex/quick/ralloc_util.cc @@ -735,7 +735,7 @@ void Mir2Lir::FlushRegWide(RegStorage reg) { } int v_reg = mir_graph_->SRegToVReg(info1->SReg()); ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); - StoreBaseDisp(TargetReg(kSp), VRegOffset(v_reg), reg, k64, kNotVolatile); + StoreBaseDisp(TargetReg(kSp), VRegOffset(v_reg), reg, k64); } } else { RegisterInfo* info = GetRegInfo(reg); @@ -743,7 +743,7 @@ void Mir2Lir::FlushRegWide(RegStorage reg) { info->SetIsDirty(false); int v_reg = mir_graph_->SRegToVReg(info->SReg()); ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); - StoreBaseDisp(TargetReg(kSp), VRegOffset(v_reg), reg, k64, kNotVolatile); + StoreBaseDisp(TargetReg(kSp), VRegOffset(v_reg), reg, k64); } } } @@ -755,7 +755,7 @@ void Mir2Lir::FlushReg(RegStorage reg) { info->SetIsDirty(false); int v_reg = mir_graph_->SRegToVReg(info->SReg()); ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); - StoreBaseDisp(TargetReg(kSp), VRegOffset(v_reg), reg, kWord, kNotVolatile); + StoreBaseDisp(TargetReg(kSp), VRegOffset(v_reg), reg, kWord); } } |