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author Yixin Shou <yixin.shou@intel.com> 2014-02-07 05:09:30 -0800
committer Yixin Shou <yixin.shou@intel.com> 2014-02-07 10:08:44 -0800
commitdbb17e378b538133750e56375bbdbb217db7b248 (patch)
tree59b7ae146e75809532fdbd43b4ef177be310b772 /compiler/dex/quick/gen_invoke.cc
parent90ea00c30f5dd1a7c2934417ac5ec7d116ceb93d (diff)
Added inlined abs method with float and double type
This patch added the implementation for inlining java.lang.Math.abs() method with float and double type. Change-Id: Ic99471b4ab4176e4a0153bef383bb49944fb636f Signed-off-by: Yixin Shou <yixin.shou@intel.com>
Diffstat (limited to 'compiler/dex/quick/gen_invoke.cc')
-rw-r--r--compiler/dex/quick/gen_invoke.cc37
1 files changed, 37 insertions, 0 deletions
diff --git a/compiler/dex/quick/gen_invoke.cc b/compiler/dex/quick/gen_invoke.cc
index 3823fb31d4..d7aecaf3f5 100644
--- a/compiler/dex/quick/gen_invoke.cc
+++ b/compiler/dex/quick/gen_invoke.cc
@@ -1076,6 +1076,43 @@ bool Mir2Lir::GenInlinedAbsLong(CallInfo* info) {
}
}
+bool Mir2Lir::GenInlinedAbsFloat(CallInfo* info) {
+ if (cu_->instruction_set == kMips) {
+ // TODO - add Mips implementation
+ return false;
+ }
+ RegLocation rl_src = info->args[0];
+ rl_src = LoadValue(rl_src, kCoreReg);
+ RegLocation rl_dest = InlineTarget(info);
+ RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
+ int signMask = AllocTemp();
+ LoadConstant(signMask, 0x7fffffff);
+ OpRegRegReg(kOpAnd, rl_result.low_reg, rl_src.low_reg, signMask);
+ FreeTemp(signMask);
+ StoreValue(rl_dest, rl_result);
+ return true;
+}
+
+bool Mir2Lir::GenInlinedAbsDouble(CallInfo* info) {
+ if (cu_->instruction_set == kMips) {
+ // TODO - add Mips implementation
+ return false;
+ }
+ RegLocation rl_src = info->args[0];
+ rl_src = LoadValueWide(rl_src, kCoreReg);
+ RegLocation rl_dest = InlineTargetWide(info);
+ RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
+ OpRegCopyWide(rl_result.low_reg, rl_result.high_reg, rl_src.low_reg, rl_src.high_reg);
+ FreeTemp(rl_src.low_reg);
+ FreeTemp(rl_src.high_reg);
+ int signMask = AllocTemp();
+ LoadConstant(signMask, 0x7fffffff);
+ OpRegReg(kOpAnd, rl_result.high_reg, signMask);
+ FreeTemp(signMask);
+ StoreValueWide(rl_dest, rl_result);
+ return true;
+}
+
bool Mir2Lir::GenInlinedFloatCvt(CallInfo* info) {
if (cu_->instruction_set == kMips) {
// TODO - add Mips implementation