diff options
| author | 2014-01-24 18:50:23 +0000 | |
|---|---|---|
| committer | 2014-01-24 18:50:23 +0000 | |
| commit | a278ac31a1beeebd093ec64026d27a02fdc28807 (patch) | |
| tree | 20924b0b7bd64dec22724514fcdf4ff2656bf24c /compiler/dex/quick/gen_common.cc | |
| parent | 57103556271b1cab119a1f0470f113c8b32cd375 (diff) | |
| parent | 2bf31e67694da24a19fc1f328285cebb1a4b9964 (diff) | |
Merge "Improve x86 long divide"
Diffstat (limited to 'compiler/dex/quick/gen_common.cc')
| -rw-r--r-- | compiler/dex/quick/gen_common.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/compiler/dex/quick/gen_common.cc b/compiler/dex/quick/gen_common.cc index f2807c6209..1f00b2a6a5 100644 --- a/compiler/dex/quick/gen_common.cc +++ b/compiler/dex/quick/gen_common.cc @@ -1382,6 +1382,9 @@ void Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, } rl_result = GenDivRem(rl_dest, rl_src1.low_reg, rl_src2.low_reg, op == kOpDiv); done = true; + } else if (cu_->instruction_set == kX86) { + rl_result = GenDivRem(rl_dest, rl_src1, rl_src2, op == kOpDiv, check_zero); + done = true; } else if (cu_->instruction_set == kThumb2) { if (cu_->GetInstructionSetFeatures().HasDivideInstruction()) { // Use ARM SDIV instruction for division. For remainder we also need to @@ -1650,6 +1653,9 @@ void Mir2Lir::GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, Re rl_src = LoadValue(rl_src, kCoreReg); rl_result = GenDivRemLit(rl_dest, rl_src.low_reg, lit, is_div); done = true; + } else if (cu_->instruction_set == kX86) { + rl_result = GenDivRemLit(rl_dest, rl_src, lit, is_div); + done = true; } else if (cu_->instruction_set == kThumb2) { if (cu_->GetInstructionSetFeatures().HasDivideInstruction()) { // Use ARM SDIV instruction for division. For remainder we also need to |