diff options
| author | 2015-02-24 16:55:04 +0100 | |
|---|---|---|
| committer | 2015-03-06 13:05:47 -0800 | |
| commit | 6ea651f0f4c7de4580beb2e887d86802c1ae0738 (patch) | |
| tree | fd97dcbd7301892cb785ca34aee21ad86437c3b3 /compiler/dex/quick/codegen_util.cc | |
| parent | 0e242b5cad3c0b68b72f28c1e5fd3fdd4c05bfd8 (diff) | |
Initial support for quick compiler on MIPS64r6.
Change-Id: I6f43027b84e4a98ea320cddb972d9cf39bf7c4f8
Diffstat (limited to 'compiler/dex/quick/codegen_util.cc')
| -rw-r--r-- | compiler/dex/quick/codegen_util.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/compiler/dex/quick/codegen_util.cc b/compiler/dex/quick/codegen_util.cc index 0bac511dd1..029c0ca8c0 100644 --- a/compiler/dex/quick/codegen_util.cc +++ b/compiler/dex/quick/codegen_util.cc @@ -541,6 +541,7 @@ void Mir2Lir::InstallSwitchTables() { break; case kArm64: case kMips: + case kMips64: bx_offset = tab_rec->anchor->offset; break; default: LOG(FATAL) << "Unexpected instruction set: " << cu_->instruction_set; @@ -1203,6 +1204,7 @@ void Mir2Lir::LoadCodeAddress(const MethodReference& target_method, InvokeType t LIR* load_pc_rel = OpPcRelLoad(TargetPtrReg(symbolic_reg), data_target); AppendLIR(load_pc_rel); DCHECK_NE(cu_->instruction_set, kMips) << reinterpret_cast<void*>(data_target); + DCHECK_NE(cu_->instruction_set, kMips64) << reinterpret_cast<void*>(data_target); } void Mir2Lir::LoadMethodAddress(const MethodReference& target_method, InvokeType type, @@ -1220,6 +1222,7 @@ void Mir2Lir::LoadMethodAddress(const MethodReference& target_method, InvokeType LIR* load_pc_rel = OpPcRelLoad(TargetReg(symbolic_reg, kRef), data_target); AppendLIR(load_pc_rel); DCHECK_NE(cu_->instruction_set, kMips) << reinterpret_cast<void*>(data_target); + DCHECK_NE(cu_->instruction_set, kMips64) << reinterpret_cast<void*>(data_target); } void Mir2Lir::LoadClassType(const DexFile& dex_file, uint32_t type_idx, |