Update load/store utilities for 64-bit backends

This CL replaces the typical use of LoadWord/StoreWord
utilities (which, in practice, were 32-bit load/store) in
favor of a new set that make the size explicit.  We now have:

   LoadWordDisp/StoreWordDisp:
    32 or 64 depending on target.  Load or store the natural
    word size.  Expect this to be used infrequently - generally
    when we know we're dealing with a native pointer or flushed
    register not holding a Dalvik value (Dalvik values will flush
    to home location sizes based on Dalvik, rather than the target).

   Load32Disp/Store32Disp:
     Load or store 32 bits, regardless of target.

   Load64Disp/Store64Disp:
     Load or store 64 bits, regardless of target.

   LoadRefDisp:
     Load a 32-bit compressed reference, and expand it to the
     natural word size in the target register.

   StoreRefDisp:
     Compress a reference held in a register of the natural word
     size and store it as a 32-bit compressed reference.

Change-Id: I50fcbc8684476abd9527777ee7c152c61ba41c6f

1 files changed, 1 insertions, 1 deletions

diff --git a/compiler/dex/quick/codegen_util.cc b/compiler/dex/quick/codegen_util.cc
index 6e6b8f0a30..9d85477510 100644
--- a/compiler/dex/quick/codegen_util.cc
+++ b/compiler/dex/quick/codegen_util.cc
@@ -1118,7 +1118,7 @@ bool Mir2Lir::BadOverlap(RegLocation rl_src, RegLocation rl_dest) {
 LIR *Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
                                 int offset, int check_value, LIR* target) {
   // Handle this for architectures that can't compare to memory.
-  LoadWordDisp(base_reg, offset, temp_reg);
+  Load32Disp(base_reg, offset, temp_reg);
   LIR* branch = OpCmpImmBranch(cond, temp_reg, check_value, target);
   return branch;
 }