diff options
| author | 2015-06-16 17:57:37 +0600 | |
|---|---|---|
| committer | 2015-06-17 16:28:57 +0600 | |
| commit | 41f9cc28f2c9edd3903ba6ca1c75b022445552ad (patch) | |
| tree | 92e485e7bbf4e43ef4e40fd2824610074888a8ce /compiler/dex/quick/codegen_util.cc | |
| parent | c4977a58b1feca22a83fd5239aa266c7ce16ab87 (diff) | |
ART: Compiler generated GC map should take care of temp registers.
If the compiler use a temp register as a reference it should be
added to generated GC map along with other SSA regs.
Change-Id: I3c79896dcd72228c9cf2bbbe737642d9ffb7684d
Signed-off-by: Pavel Vyssotski <pavel.n.vyssotski@intel.com>
Diffstat (limited to 'compiler/dex/quick/codegen_util.cc')
| -rw-r--r-- | compiler/dex/quick/codegen_util.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/compiler/dex/quick/codegen_util.cc b/compiler/dex/quick/codegen_util.cc index c803e6588c..8629f39702 100644 --- a/compiler/dex/quick/codegen_util.cc +++ b/compiler/dex/quick/codegen_util.cc @@ -1370,7 +1370,9 @@ void Mir2Lir::InitReferenceVRegs(BasicBlock* bb, BitVector* references) { DCHECK(first_bb->data_flow_info->vreg_to_ssa_map_exit != nullptr); const int32_t* first_vreg_to_ssa_map = first_bb->data_flow_info->vreg_to_ssa_map_exit; references->ClearAllBits(); - for (uint32_t vreg = 0, num_vregs = mir_graph_->GetNumOfCodeVRs(); vreg != num_vregs; ++vreg) { + for (uint32_t vreg = 0, + num_vregs = mir_graph_->GetNumOfCodeVRs() + mir_graph_->GetNumUsedCompilerTemps(); + vreg != num_vregs; ++vreg) { int32_t sreg = first_vreg_to_ssa_map[vreg]; if (sreg != INVALID_SREG && mir_graph_->reg_location_[sreg].ref && !mir_graph_->IsConstantNullRef(mir_graph_->reg_location_[sreg])) { |