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author Ian Rogers <irogers@google.com> 2013-10-11 08:44:13 -0700
committer Ian Rogers <irogers@google.com> 2013-10-11 08:44:13 -0700
commit41cdd43bd6968a06b1344efdd57ccf302f997a0e (patch)
tree82cb81b241a3dd8bfe845c057c9b37f0f917cde6 /compiler/dex/mir_optimization.cc
parent775c496f989f0e37d2e9a43274c0b55f201b4116 (diff)
Disable select instruction generation on ARM.
Change-Id: I114547d44605b06b2fed396b2fbad03935f66ebc
Diffstat (limited to 'compiler/dex/mir_optimization.cc')
-rw-r--r--compiler/dex/mir_optimization.cc3
1 files changed, 2 insertions, 1 deletions
diff --git a/compiler/dex/mir_optimization.cc b/compiler/dex/mir_optimization.cc
index 05e428e178..0b4f04100b 100644
--- a/compiler/dex/mir_optimization.cc
+++ b/compiler/dex/mir_optimization.cc
@@ -325,7 +325,8 @@ bool MIRGraph::BasicBlockOpt(BasicBlock* bb) {
// Is this the select pattern?
// TODO: flesh out support for Mips and X86. NOTE: llvm's select op doesn't quite work here.
// TUNING: expand to support IF_xx compare & branches
- if (!(cu_->compiler_backend == kPortable) && (cu_->instruction_set == kThumb2) &&
+ if (false &&
+ !(cu_->compiler_backend == kPortable) && (cu_->instruction_set == kThumb2) &&
((mir->dalvikInsn.opcode == Instruction::IF_EQZ) ||
(mir->dalvikInsn.opcode == Instruction::IF_NEZ))) {
BasicBlock* ft = bb->fall_through;