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author | 2014-07-09 07:44:21 +0000 | |
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committer | 2014-07-08 22:56:31 +0000 | |
commit | 2cfe30bd592cb6ae63bb4c28ccaf4b069d6ab565 (patch) | |
tree | 3eb01d4c9f9a36985f70450822c0bb3f4065db02 /compiler/dex/mir_dataflow.cc | |
parent | 7b68fb3b9b421d4b20c1993704986d637f1cab91 (diff) | |
parent | 60bfe7b3e8f00f0a8ef3f5d8716adfdf86b71f43 (diff) |
Merge "X86 Backend support for vectorized float and byte 16x16 operations"
Diffstat (limited to 'compiler/dex/mir_dataflow.cc')
-rw-r--r-- | compiler/dex/mir_dataflow.cc | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/compiler/dex/mir_dataflow.cc b/compiler/dex/mir_dataflow.cc index 9fea709568..bc99a272a6 100644 --- a/compiler/dex/mir_dataflow.cc +++ b/compiler/dex/mir_dataflow.cc @@ -840,6 +840,54 @@ const uint64_t MIRGraph::oat_data_flow_attributes_[kMirOpLast] = { // 113 MIR_SELECT DF_DA | DF_UB, + + // 114 MirOpConstVector + DF_DA, + + // 115 MirOpMoveVector + 0, + + // 116 MirOpPackedMultiply + 0, + + // 117 MirOpPackedAddition + 0, + + // 118 MirOpPackedSubtract + 0, + + // 119 MirOpPackedShiftLeft + 0, + + // 120 MirOpPackedSignedShiftRight + 0, + + // 121 MirOpPackedUnsignedShiftRight + 0, + + // 122 MirOpPackedAnd + 0, + + // 123 MirOpPackedOr + 0, + + // 124 MirOpPackedXor + 0, + + // 125 MirOpPackedAddReduce + DF_DA | DF_UA, + + // 126 MirOpPackedReduce + DF_DA, + + // 127 MirOpPackedSet + DF_UB, + + // 128 MirOpReserveVectorRegisters + 0, + + // 129 MirOpReturnVectorRegisters + 0, }; /* Return the base virtual register for a SSA name */ |