riscv64: cmpl-float, cmpg-float, cmpl-double, cmpg-double, cmp-long

(1) setup
  lunch aosp_riscv64-trunk-userdebug

  export ART_TEST_SSH_USER=ubuntu
  export ART_TEST_SSH_HOST=localhost
  export ART_TEST_SSH_PORT=10001
  export ART_TEST_ON_VM=true

  . art/tools/buildbot-utils.sh
  art/tools/buildbot-build.sh --target

  # Create, boot and configure the VM.
  art/tools/buildbot-vm.sh create
  art/tools/buildbot-vm.sh boot
  art/tools/buildbot-vm.sh setup-ssh  # password: 'ubuntu'

  art/tools/buildbot-cleanup-device.sh
  art/tools/buildbot-setup-device.sh
  art/tools/buildbot-sync.sh

(2) test
  art/test.py --target -r --no-prebuild --ndebug --64  -j 12 --cdex-none --interpreter

Test: Run these opcodes against all interpreter
tests on a Linux RISC-V VM.

Test: Cuttlefish boot

Bug: 283082047

Change-Id: I70ee24c404da0820419e4a49f30a26783e00cda1

3 files changed, 80 insertions, 10 deletions

diff --git a/runtime/interpreter/mterp/riscv64/control_flow.S b/runtime/interpreter/mterp/riscv64/control_flow.S
index 3c8a06267c..e41c7e037e 100644
--- a/runtime/interpreter/mterp/riscv64/control_flow.S
+++ b/runtime/interpreter/mterp/riscv64/control_flow.S
@@ -58,6 +58,24 @@
    call art_quick_deliver_exception  // args a0, a1
    unimp
 
+// cmp-long vAA, vBB, vCC
+// Format 23x: AA|31 CC|BB
+%def op_cmp_long():
+   FETCH t1, count=1     // t1 := CC|BB
+   srliw t0, xINST, 8    // t0 := AA
+   srliw t2, t1, 8       // t2 := CC
+   andi t1, t1, 0xFF     // t1 := BB
+   GET_VREG_WIDE t1, t1  // t1 := fp[BB]
+   GET_VREG_WIDE t2, t2  // t2 := fp[CC]
+   // Note: Formula "(SLT r,l) - (SLT l,r)" lifted from compiler.
+   slt t3, t1, t2
+   slt t4, t2, t1
+   sub t4, t4, t3
+   FETCH_ADVANCE_INST 2
+%  set_vreg("t4", "t0", z0="t1")  # fp[AA] := t4
+   GET_INST_OPCODE t0
+   GOTO_OPCODE t0
+
 %def bincmp(condition=""):
     unimp
 
@@ -73,9 +91,6 @@
 %def op_goto_32():
     unimp
 
-%def op_cmp_long():
-    unimp
-
 %def op_if_eq():
 %  bincmp(condition="eq")
 
diff --git a/runtime/interpreter/mterp/riscv64/floating_point.S b/runtime/interpreter/mterp/riscv64/floating_point.S
index f7bdd69eb5..4a2ae215f3 100644
--- a/runtime/interpreter/mterp/riscv64/floating_point.S
+++ b/runtime/interpreter/mterp/riscv64/floating_point.S
@@ -1,17 +1,67 @@
 // Note: Floating point operations must follow IEEE 754 rules, using round-to-nearest and gradual
 // underflow, except where stated otherwise.
 
-%def op_cmpl_float():
-    unimp
-
-%def op_cmpg_float():
-    unimp
+//
+// floating-point comparators vAA, vBB, vCC
+// Note: Perform the indicated floating point comparison, setting a to 0 if b == c, 1 if b > c, or
+// -1 if b < c. The "bias" listed indicates how NaN comparisons are treated: "gt bias" instructions
+// return 1 for NaN comparisons, and "lt bias" instructions return -1.
+//
 
+// cmpl-float vAA, vBB, vCC
+// Format 23x: AA|2d CC|BB
+// LT bias, if NaN then vAA := -1
+%def op_cmpl_float(is_double=False):
+   FETCH t1, count=1     // t1 := CC|BB
+   srliw t0, xINST, 8    // t0 := AA
+   srliw t2, t1, 8       // t2 := CC
+   andi t1, t1, 0xFF     // t1 := BB
+%  get_vreg_float("ft1", "t1", is_double=is_double)  # ft1 := fp[BB]
+%  get_vreg_float("ft2", "t2", is_double=is_double)  # ft2 := fp[CC]
+   // Note: Formula "((FLE r,l) - 1) + (FLT r,l)" lifted from compiler.
+%  precision = "d" if is_double else "s"
+   fle.${precision} t1, ft2, ft1
+   flt.${precision} t2, ft2, ft1
+   addi t1, t1, -1
+   add t2, t2, t1
+   FETCH_ADVANCE_INST 2
+%  set_vreg("t2", "t0", z0="t1")  # fp[AA] := result
+   GET_INST_OPCODE t0
+   GOTO_OPCODE t0
+
+// cmpg-float vvAA, vBB, vCC
+// Format 23x: AA|2e CC|BB
+// GT bias, if NaN then vAA := 1
+%def op_cmpg_float(is_double=False):
+   FETCH t1, count=1     // t1 := CC|BB
+   srliw t0, xINST, 8    // t0 := AA
+   srliw t2, t1, 8       // t2 := CC
+   andi t1, t1, 0xFF     // t1 := BB
+%  get_vreg_float("ft1", "t1", is_double=is_double)  # ft1 := fp[BB]
+%  get_vreg_float("ft2", "t2", is_double=is_double)  # ft2 := fp[CC]
+   // Note: Formula "((FLE l,r) ^ 1) - (FLT l,r)" lifted from compiler.
+%  precision = "d" if is_double else "s"
+   fle.${precision} t1, ft1, ft2
+   flt.${precision} t2, ft1, ft2
+   xori t1, t1, 1
+   sub t2, t1, t2
+   FETCH_ADVANCE_INST 2
+%  set_vreg("t2", "t0", z0="t1")  # fp[AA] := result
+   GET_INST_OPCODE t0
+   GOTO_OPCODE t0
+
+// cmpl-double vAA, vBB, vCC
+// Format 23x: AA|2f CC|BB
+// LT bias, if NaN then vAA := -1
 %def op_cmpl_double():
-    unimp
+%  op_cmpl_float(is_double=True)
 
+// cmpg-double vAA, vBB, vCC
+// Format 23x: AA|30 CC|BB
+// Note: Formula "((FLE l,r) ^ 1) - (FLT l,r)" lifted from compiler.
+// GT bias, if NaN then vAA := 1
 %def op_cmpg_double():
-    unimp
+%  op_cmpg_float(is_double=True)
 
 //
 // funop vA, vB
diff --git a/runtime/nterp_helpers.cc b/runtime/nterp_helpers.cc
index 55e58c5d84..e0624af2ca 100644
--- a/runtime/nterp_helpers.cc
+++ b/runtime/nterp_helpers.cc
@@ -286,6 +286,11 @@ bool CanMethodUseNterp(ArtMethod* method, InstructionSet isa) {
         case Instruction::FILLED_NEW_ARRAY_RANGE:
         case Instruction::FILL_ARRAY_DATA:
         case Instruction::THROW:
+        case Instruction::CMPL_FLOAT:
+        case Instruction::CMPG_FLOAT:
+        case Instruction::CMPL_DOUBLE:
+        case Instruction::CMPG_DOUBLE:
+        case Instruction::CMP_LONG:
         case Instruction::AGET:
         case Instruction::AGET_WIDE:
         case Instruction::AGET_OBJECT: