diff options
| author | 2022-09-28 16:06:15 +0100 | |
|---|---|---|
| committer | 2024-03-22 08:54:34 +0000 | |
| commit | c4b188db0eb42d9639e5f66d0d063105024f8960 (patch) | |
| tree | 8e1bbd22b0e20f1fe739eb8cf6133bedf3088ac2 | |
| parent | f4ca2830f238ec7673392389d999bfe98283a459 (diff) | |
Don't use predicated vectorization by default.
This patch sets the traditional vectorization mode to be
the default one; previously, if the target supported
predicated vectorization (e.g. arm64 SVE), predicated
vectorization was be tried for ALL loops.
Motivation: this is a prerequisite for the further patches
to enable mixed mode vectorization - when most of the loops
are vectorized in traditional mode and some others - in
predicated.
A new env variable - ART_FORCE_TRY_PREDICATED_SIMD - is
introduced to force-use the predicated mode; this could be
set to true for testing purposes.
Checker tests are adjusted accordingly - to also check the
ART_FORCE_TRY_PREDICATED_SIMD variable.
Test: test-art-target, test-art-host.
Test: test-art-target with ART_FORCE_TRY_PREDICATED_SIMD=true.
Original author: Artem Serov <Artem.Serov@linaro.org>
Test: ./art/test/testrunner/testrunner.py --host --optimizing --jit
Test: ./art/test/testrunner/testrunner.py --target --optimizing --jit
(with ART_FORCE_TRY_PREDICATED_SIMD=true and without)
Test: 661-checker-simd-cf-loops.
Test: target tests on arm64 with SVE
Change-Id: I57852f3777da6f86d615429d1a3c703cb87fbac8
31 files changed, 211 insertions, 200 deletions
diff --git a/build/art.go b/build/art.go index 34e3c159e3..0e06c62979 100644 --- a/build/art.go +++ b/build/art.go @@ -82,6 +82,10 @@ func globalFlags(ctx android.LoadHookContext) ([]string, []string) { cflags = append(cflags, "-DART_USE_TLAB=1") } + if ctx.Config().IsEnvTrue("ART_FORCE_TRY_PREDICATED_SIMD") { + cflags = append(cflags, "-DART_FORCE_TRY_PREDICATED_SIMD=1") + } + // We need larger stack overflow guards for ASAN, as the compiled code will have // larger frame sizes. For simplicity, just use global not-target-specific cflags. // Note: We increase this for both debug and non-debug, as the overflow gap will diff --git a/compiler/optimizing/loop_optimization.cc b/compiler/optimizing/loop_optimization.cc index ed66d65373..14e6683cf8 100644 --- a/compiler/optimizing/loop_optimization.cc +++ b/compiler/optimizing/loop_optimization.cc @@ -875,6 +875,13 @@ static HBasicBlock* GetInnerLoopFiniteSingleExit(HLoopInformation* loop_info) { return exit; } +// Determines whether predicated loop vectorization should be tried for ALL loops. +#ifdef ART_FORCE_TRY_PREDICATED_SIMD + static constexpr bool kForceTryPredicatedSIMD = true; +#else + static constexpr bool kForceTryPredicatedSIMD = false; +#endif + bool HLoopOptimization::TryOptimizeInnerLoopFinite(LoopNode* node) { HBasicBlock* header = node->loop_info->GetHeader(); HBasicBlock* preheader = node->loop_info->GetPreHeader(); @@ -931,7 +938,7 @@ bool HLoopOptimization::TryOptimizeInnerLoopFinite(LoopNode* node) { return false; } - if (IsInPredicatedVectorizationMode()) { + if (kForceTryPredicatedSIMD && IsInPredicatedVectorizationMode()) { return TryVectorizePredicated(node, body, exit, main_phi, trip_count); } else { return TryVectorizedTraditional(node, body, exit, main_phi, trip_count); diff --git a/test/527-checker-array-access-simd/src/Main.java b/test/527-checker-array-access-simd/src/Main.java index a08b1f09b4..a26efaeefe 100644 --- a/test/527-checker-array-access-simd/src/Main.java +++ b/test/527-checker-array-access-simd/src/Main.java @@ -25,7 +25,7 @@ public class Main { /// CHECK-START-ARM64: void Main.checkIntCase(int[]) instruction_simplifier_arm64 (before) /// CHECK-DAG: <<Array:l\d+>> ParameterValue /// CHECK-DAG: <<Const5:i\d+>> IntConstant 5 - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Const5>>,{{j\d+}}] // -------------- Loop @@ -51,7 +51,7 @@ public class Main { /// CHECK-START-ARM64: void Main.checkIntCase(int[]) instruction_simplifier_arm64 (after) /// CHECK-DAG: <<Array:l\d+>> ParameterValue /// CHECK-DAG: <<Const5:i\d+>> IntConstant 5 - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // IntermediateAddressIndex is not supported for SVE. /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Const5>>,{{j\d+}}] @@ -84,7 +84,7 @@ public class Main { /// CHECK-START-ARM64: void Main.checkIntCase(int[]) GVN$after_arch (after) /// CHECK-DAG: <<Array:l\d+>> ParameterValue /// CHECK-DAG: <<Const5:i\d+>> IntConstant 5 - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // IntermediateAddressIndex is not supported for SVE. /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Const5>>,{{j\d+}}] @@ -114,7 +114,7 @@ public class Main { /// CHECK-FI: /// CHECK-START-ARM64: void Main.checkIntCase(int[]) disassembly (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // IntermediateAddressIndex is not supported for SVE. /// CHECK-NOT: IntermediateAddressIndex @@ -134,7 +134,7 @@ public class Main { /// CHECK-START-ARM64: void Main.checkByteCase(byte[]) instruction_simplifier_arm64 (before) /// CHECK-DAG: <<Array:l\d+>> ParameterValue /// CHECK-DAG: <<Const5:i\d+>> IntConstant 5 - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Const5>>,{{j\d+}}] // -------------- Loop @@ -161,7 +161,7 @@ public class Main { /// CHECK-DAG: <<Array:l\d+>> ParameterValue /// CHECK-DAG: <<Const0:i\d+>> IntConstant 0 /// CHECK-DAG: <<Const5:i\d+>> IntConstant 5 - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // IntermediateAddressIndex is not supported for SVE. /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Const5>>,{{j\d+}}] @@ -194,7 +194,7 @@ public class Main { /// CHECK-DAG: <<Array:l\d+>> ParameterValue /// CHECK-DAG: <<Const0:i\d+>> IntConstant 0 /// CHECK-DAG: <<Const5:i\d+>> IntConstant 5 - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // IntermediateAddressIndex is not supported for SVE. /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Const5>>,{{j\d+}}] @@ -223,7 +223,7 @@ public class Main { /// CHECK-FI: /// CHECK-START-ARM64: void Main.checkByteCase(byte[]) disassembly (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // IntermediateAddressIndex is not supported for SVE. /// CHECK-NOT: IntermediateAddressIndex @@ -247,7 +247,7 @@ public class Main { /// CHECK-START-ARM64: void Main.checkSingleAccess(int[]) instruction_simplifier_arm64 (before) /// CHECK-DAG: <<Array:l\d+>> ParameterValue /// CHECK-DAG: <<Const5:i\d+>> IntConstant 5 - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Const5>>,{{j\d+}}] // -------------- Loop @@ -270,7 +270,7 @@ public class Main { /// CHECK-DAG: <<Array:l\d+>> ParameterValue /// CHECK-DAG: <<Const0:i\d+>> IntConstant 0 /// CHECK-DAG: <<Const5:i\d+>> IntConstant 5 - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Const5>>,{{j\d+}}] // -------------- Loop @@ -301,7 +301,7 @@ public class Main { /// CHECK-DAG: <<Array1:l\d+>> ParameterValue /// CHECK-DAG: <<Array2:l\d+>> ParameterValue // -------------- Loop - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<LoopP:j\d+>> VecPredWhile /// CHECK-DAG: <<Index:i\d+>> Phi @@ -323,7 +323,7 @@ public class Main { /// CHECK-START-ARM64: void Main.checkInt2Float(int[], float[]) instruction_simplifier_arm64 (after) /// CHECK-DAG: <<Array1:l\d+>> ParameterValue /// CHECK-DAG: <<Array2:l\d+>> ParameterValue - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // IntermediateAddressIndex is not supported for SVE. // -------------- Loop @@ -354,7 +354,7 @@ public class Main { /// CHECK-START-ARM64: void Main.checkInt2Float(int[], float[]) GVN$after_arch (after) /// CHECK-DAG: <<Array1:l\d+>> ParameterValue /// CHECK-DAG: <<Array2:l\d+>> ParameterValue - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // IntermediateAddressIndex is not supported for SVE. // -------------- Loop @@ -383,7 +383,7 @@ public class Main { /// CHECK-FI: /// CHECK-START-ARM64: void Main.checkInt2Float(int[], float[]) disassembly (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // IntermediateAddressIndex is not supported for SVE. /// CHECK-NOT: IntermediateAddressIndex diff --git a/test/530-checker-lse-simd/src/Main.java b/test/530-checker-lse-simd/src/Main.java index ec2faf51ec..c9be5a6440 100644 --- a/test/530-checker-lse-simd/src/Main.java +++ b/test/530-checker-lse-simd/src/Main.java @@ -38,7 +38,7 @@ public class Main { /// CHECK-NEXT: Sub /// CHECK-NEXT: Mul /// CHECK-NEXT: ArraySet - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-NEXT: ArrayGet // @@ -94,7 +94,7 @@ public class Main { /// CHECK-NEXT: ArrayGet /// CHECK-NEXT: Mul /// CHECK-NEXT: ArraySet - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-NEXT: ArrayGet // @@ -134,7 +134,7 @@ public class Main { /// CHECK-NEXT: Return /// CHECK-START: double Main.$noinline$test03(int) load_store_elimination (after) - /// CHECK-IF: not hasIsaFeature("sve") + /// CHECK-IF: not (hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true') // /// CHECK-NOT: ArrayGet loop:none // @@ -172,7 +172,7 @@ public class Main { /// CHECK: Goto loop:{{B\d+}} /// CHECK-START-ARM64: double[] Main.$noinline$test04(int) load_store_elimination (after) - /// CHECK-IF: not hasIsaFeature("sve") + /// CHECK-IF: not (hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true') // // In NEON case there is a post-loop which prevents the store to be removed. /// CHECK: VecStore @@ -185,7 +185,7 @@ public class Main { /// CHECK: Goto loop:{{B\d+}} // - /// CHECK-IF: not hasIsaFeature("sve") + /// CHECK-IF: not (hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true') // /// CHECK-NOT: VecStore // @@ -272,7 +272,7 @@ public class Main { /// CHECK: VecAdd /// CHECK: VecStore // - /// CHECK-IF: not hasIsaFeature("sve") + /// CHECK-IF: not (hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true') // /// CHECK-NOT: VecStore // diff --git a/test/530-checker-lse/src/Main.java b/test/530-checker-lse/src/Main.java index 875444941d..2516129c6c 100644 --- a/test/530-checker-lse/src/Main.java +++ b/test/530-checker-lse/src/Main.java @@ -2852,7 +2852,7 @@ public class Main { /// CHECK-START: int Main.testLoop15(int) load_store_elimination (before) /// CHECK-DAG: NewArray - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: VecPredWhile /// CHECK-DAG: VecStore @@ -2867,7 +2867,7 @@ public class Main { /// CHECK-START: int Main.testLoop15(int) load_store_elimination (after) /// CHECK-DAG: NewArray - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: VecPredWhile /// CHECK-DAG: VecStore diff --git a/test/623-checker-loop-regressions/src/Main.java b/test/623-checker-loop-regressions/src/Main.java index 2b280bb7d6..134e90c6c5 100644 --- a/test/623-checker-loop-regressions/src/Main.java +++ b/test/623-checker-loop-regressions/src/Main.java @@ -290,7 +290,7 @@ public class Main { /// CHECK-NOT: VecLoad // /// CHECK-START-ARM64: void Main.string2Bytes(char[], java.lang.String) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // TODO: Support CharAt for SVE. /// CHECK-NOT: VecLoad @@ -314,7 +314,7 @@ public class Main { /// CHECK-NOT: VecLoad /// CHECK-START-ARM64: void Main.$noinline$stringToShorts(short[], java.lang.String) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // TODO: Support CharAt for SVE. /// CHECK-NOT: VecLoad @@ -368,7 +368,7 @@ public class Main { // /// CHECK-START-ARM64: void Main.oneBoth(short[], char[]) loop_optimization (after) /// CHECK-DAG: <<One:i\d+>> IntConstant 1 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<One>>,{{j\d+}}] loop:none /// CHECK-DAG: <<LoopP:j\d+>> VecPredWhile loop:<<Loop:B\d+>> outer_loop:none @@ -423,7 +423,7 @@ public class Main { // /// CHECK-START-ARM64: void Main.typeConv(byte[], byte[]) loop_optimization (after) /// CHECK-DAG: <<One:i\d+>> IntConstant 1 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<One>>,{{j\d+}}] loop:none /// CHECK-DAG: <<LoopP:j\d+>> VecPredWhile loop:<<Loop1:B\d+>> outer_loop:none @@ -765,7 +765,7 @@ public class Main { /// CHECK-DAG: VecStore // /// CHECK-START-ARM64: int Main.testSADAndSet(int[], int[], int[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // VecSADAccumulate is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -793,7 +793,7 @@ public class Main { /// CHECK-DAG: VecSADAccumulate // /// CHECK-START-ARM64: int Main.testSADAndSAD(int[], int[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // VecSADAccumulate is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -860,7 +860,7 @@ public class Main { /// CHECK-DAG: VecSADAccumulate // /// CHECK-START-ARM64: int Main.testSADAndSADExtraAbs0(int[], int[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // VecSADAccumulate is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -894,7 +894,7 @@ public class Main { /// CHECK-DAG: VecSADAccumulate // /// CHECK-START-ARM64: int Main.testSADAndSADExtraAbs1(int[], int[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // VecSADAccumulate is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -923,7 +923,7 @@ public class Main { // Idioms common sub-expression bug: SAD and DotProd combined. // /// CHECK-START-ARM64: int Main.testSADAndDotProdCombined0(byte[], byte[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // VecSADAccumulate is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -951,7 +951,7 @@ public class Main { // Idioms common sub-expression bug: SAD and DotProd combined (reversed order). /// CHECK-START-ARM64: int Main.testSADAndDotProdCombined1(byte[], byte[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // VecSADAccumulate is not supported for SVE. /// CHECK-NOT: VecSADAccumulate diff --git a/test/640-checker-simd/src/SimdInt.java b/test/640-checker-simd/src/SimdInt.java index 065fc49c40..9bc475ca87 100644 --- a/test/640-checker-simd/src/SimdInt.java +++ b/test/640-checker-simd/src/SimdInt.java @@ -163,7 +163,7 @@ public class SimdInt { /// CHECK-DAG: ArraySet [{{l\d+}},{{i\d+}},<<Get>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-{ARM,ARM64}: void SimdInt.shr32() loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Get:d\d+>> VecLoad loop:<<Loop:B\d+>> outer_loop:none /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<Get>>,{{j\d+}}] loop:<<Loop>> outer_loop:none @@ -194,7 +194,7 @@ public class SimdInt { // /// CHECK-START-{ARM,ARM64}: void SimdInt.shr33() loop_optimization (after) /// CHECK-DAG: <<Dist:i\d+>> IntConstant 1 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Get:d\d+>> VecLoad loop:<<Loop:B\d+>> outer_loop:none /// CHECK-DAG: <<UShr:d\d+>> VecUShr [<<Get>>,<<Dist>>,{{j\d+}}] loop:<<Loop>> outer_loop:none @@ -226,7 +226,7 @@ public class SimdInt { // /// CHECK-START-{ARM,ARM64}: void SimdInt.shrMinus254() loop_optimization (after) /// CHECK-DAG: <<Dist:i\d+>> IntConstant 2 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Get:d\d+>> VecLoad loop:<<Loop:B\d+>> outer_loop:none /// CHECK-DAG: <<UShr:d\d+>> VecUShr [<<Get>>,<<Dist>>,{{j\d+}}] loop:<<Loop>> outer_loop:none diff --git a/test/640-checker-simd/src/SimdLong.java b/test/640-checker-simd/src/SimdLong.java index 13ea9afa48..3ee3e05dd1 100644 --- a/test/640-checker-simd/src/SimdLong.java +++ b/test/640-checker-simd/src/SimdLong.java @@ -58,7 +58,7 @@ public class SimdLong { // Not directly supported for longs. // /// CHECK-START-ARM64: void SimdLong.mul(long) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: VecLoad loop:<<Loop:B\d+>> outer_loop:none /// CHECK-DAG: VecMul loop:<<Loop>> outer_loop:none @@ -173,7 +173,7 @@ public class SimdLong { /// CHECK-DAG: ArraySet [{{l\d+}},{{i\d+}},<<Get>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void SimdLong.shr64() loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Get:d\d+>> VecLoad loop:<<Loop:B\d+>> outer_loop:none /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<Get>>,{{j\d+}}] loop:<<Loop>> outer_loop:none @@ -204,7 +204,7 @@ public class SimdLong { // /// CHECK-START-ARM64: void SimdLong.shr65() loop_optimization (after) /// CHECK-DAG: <<Dist:i\d+>> IntConstant 1 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Get:d\d+>> VecLoad loop:<<Loop:B\d+>> outer_loop:none /// CHECK-DAG: <<UShr:d\d+>> VecUShr [<<Get>>,<<Dist>>,{{j\d+}}] loop:<<Loop>> outer_loop:none @@ -236,7 +236,7 @@ public class SimdLong { // /// CHECK-START-ARM64: void SimdLong.shrMinus254() loop_optimization (after) /// CHECK-DAG: <<Dist:i\d+>> IntConstant 2 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Get:d\d+>> VecLoad loop:<<Loop:B\d+>> outer_loop:none /// CHECK-DAG: <<UShr:d\d+>> VecUShr [<<Get>>,<<Dist>>,{{j\d+}}] loop:<<Loop>> outer_loop:none diff --git a/test/645-checker-abs-simd/src/Main.java b/test/645-checker-abs-simd/src/Main.java index 43881be416..702779a4f4 100644 --- a/test/645-checker-abs-simd/src/Main.java +++ b/test/645-checker-abs-simd/src/Main.java @@ -45,7 +45,7 @@ public class Main { /// CHECK-DAG: VecLoad loop:<<Loop1:B\d+>> outer_loop:none /// CHECK-DAG: VecAbs loop:<<Loop1>> outer_loop:none /// CHECK-DAG: VecStore loop:<<Loop1>> outer_loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: VecPredWhile loop:<<Loop1>> outer_loop:none /// CHECK-NOT: ArrayGet @@ -100,7 +100,7 @@ public class Main { /// CHECK-DAG: VecLoad loop:<<Loop1:B\d+>> outer_loop:none /// CHECK-DAG: VecAbs loop:<<Loop1>> outer_loop:none /// CHECK-DAG: VecStore loop:<<Loop1>> outer_loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: VecPredWhile loop:<<Loop1>> outer_loop:none /// CHECK-NOT: ArrayGet @@ -132,7 +132,7 @@ public class Main { /// CHECK-DAG: VecLoad loop:<<Loop1:B\d+>> outer_loop:none /// CHECK-DAG: VecAbs loop:<<Loop1>> outer_loop:none /// CHECK-DAG: VecStore loop:<<Loop1>> outer_loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: VecPredWhile loop:<<Loop1>> outer_loop:none /// CHECK-NOT: ArrayGet @@ -174,7 +174,7 @@ public class Main { /// CHECK-DAG: VecLoad loop:<<Loop1:B\d+>> outer_loop:none /// CHECK-DAG: VecAbs loop:<<Loop1>> outer_loop:none /// CHECK-DAG: VecStore loop:<<Loop1>> outer_loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: VecPredWhile loop:<<Loop1>> outer_loop:none /// CHECK-NOT: ArrayGet @@ -206,7 +206,7 @@ public class Main { /// CHECK-DAG: VecLoad loop:<<Loop1:B\d+>> outer_loop:none /// CHECK-DAG: VecAbs loop:<<Loop1>> outer_loop:none /// CHECK-DAG: VecStore loop:<<Loop1>> outer_loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: VecPredWhile loop:<<Loop1>> outer_loop:none /// CHECK-NOT: ArrayGet @@ -238,7 +238,7 @@ public class Main { /// CHECK-DAG: VecLoad loop:<<Loop1:B\d+>> outer_loop:none /// CHECK-DAG: VecAbs loop:<<Loop1>> outer_loop:none /// CHECK-DAG: VecStore loop:<<Loop1>> outer_loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: VecPredWhile loop:<<Loop1>> outer_loop:none /// CHECK-NOT: ArrayGet @@ -270,7 +270,7 @@ public class Main { /// CHECK-DAG: VecLoad loop:<<Loop1:B\d+>> outer_loop:none /// CHECK-DAG: VecAbs loop:<<Loop1>> outer_loop:none /// CHECK-DAG: VecStore loop:<<Loop1>> outer_loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: VecPredWhile loop:<<Loop1>> outer_loop:none /// CHECK-NOT: ArrayGet diff --git a/test/646-checker-simd-hadd/src/HaddAltByte.java b/test/646-checker-simd-hadd/src/HaddAltByte.java index 69d46023ff..585291f0ac 100644 --- a/test/646-checker-simd-hadd/src/HaddAltByte.java +++ b/test/646-checker-simd-hadd/src/HaddAltByte.java @@ -46,7 +46,7 @@ public class HaddAltByte { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddAltByte.halving_add_signed(byte[], byte[], byte[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -96,7 +96,7 @@ public class HaddAltByte { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddAltByte.halving_add_unsigned(byte[], byte[], byte[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -134,7 +134,7 @@ public class HaddAltByte { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddAltByte.rounding_halving_add_signed(byte[], byte[], byte[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -186,7 +186,7 @@ public class HaddAltByte { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddAltByte.rounding_halving_add_unsigned(byte[], byte[], byte[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -224,7 +224,7 @@ public class HaddAltByte { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddAltByte.halving_add_signed_constant(byte[], byte[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -274,7 +274,7 @@ public class HaddAltByte { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddAltByte.halving_add_unsigned_constant(byte[], byte[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd diff --git a/test/646-checker-simd-hadd/src/HaddAltChar.java b/test/646-checker-simd-hadd/src/HaddAltChar.java index f9d40a9d3e..62fbcece96 100644 --- a/test/646-checker-simd-hadd/src/HaddAltChar.java +++ b/test/646-checker-simd-hadd/src/HaddAltChar.java @@ -46,7 +46,7 @@ public class HaddAltChar { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddAltChar.halving_add_unsigned(char[], char[], char[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -97,7 +97,7 @@ public class HaddAltChar { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddAltChar.halving_add_also_unsigned(char[], char[], char[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -138,7 +138,7 @@ public class HaddAltChar { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddAltChar.rounding_halving_add_unsigned(char[], char[], char[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -191,7 +191,7 @@ public class HaddAltChar { // // /// CHECK-START-ARM64: void HaddAltChar.rounding_halving_add_also_unsigned(char[], char[], char[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -232,7 +232,7 @@ public class HaddAltChar { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddAltChar.halving_add_unsigned_constant(char[], char[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -282,7 +282,7 @@ public class HaddAltChar { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddAltChar.halving_add_also_unsigned_constant(char[], char[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd diff --git a/test/646-checker-simd-hadd/src/HaddAltShort.java b/test/646-checker-simd-hadd/src/HaddAltShort.java index 3b19a2638e..fcc52ed90c 100644 --- a/test/646-checker-simd-hadd/src/HaddAltShort.java +++ b/test/646-checker-simd-hadd/src/HaddAltShort.java @@ -46,7 +46,7 @@ public class HaddAltShort { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddAltShort.halving_add_signed(short[], short[], short[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -96,7 +96,7 @@ public class HaddAltShort { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddAltShort.halving_add_unsigned(short[], short[], short[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -136,7 +136,7 @@ public class HaddAltShort { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddAltShort.rounding_halving_add_signed(short[], short[], short[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -188,7 +188,7 @@ public class HaddAltShort { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddAltShort.rounding_halving_add_unsigned(short[], short[], short[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -228,7 +228,7 @@ public class HaddAltShort { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddAltShort.halving_add_signed_constant(short[], short[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -278,7 +278,7 @@ public class HaddAltShort { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddAltShort.halving_add_unsigned_constant(short[], short[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd diff --git a/test/646-checker-simd-hadd/src/HaddByte.java b/test/646-checker-simd-hadd/src/HaddByte.java index c8bb0aaf2b..bcf93ea402 100644 --- a/test/646-checker-simd-hadd/src/HaddByte.java +++ b/test/646-checker-simd-hadd/src/HaddByte.java @@ -43,7 +43,7 @@ public class HaddByte { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddByte.halving_add_signed(byte[], byte[], byte[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -93,7 +93,7 @@ public class HaddByte { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddByte.halving_add_unsigned(byte[], byte[], byte[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -131,7 +131,7 @@ public class HaddByte { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddByte.rounding_halving_add_signed(byte[], byte[], byte[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -183,7 +183,7 @@ public class HaddByte { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddByte.rounding_halving_add_unsigned(byte[], byte[], byte[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -221,7 +221,7 @@ public class HaddByte { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddByte.halving_add_signed_constant(byte[], byte[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -271,7 +271,7 @@ public class HaddByte { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddByte.halving_add_unsigned_constant(byte[], byte[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd diff --git a/test/646-checker-simd-hadd/src/HaddChar.java b/test/646-checker-simd-hadd/src/HaddChar.java index 236b08164f..1c8b52cbf9 100644 --- a/test/646-checker-simd-hadd/src/HaddChar.java +++ b/test/646-checker-simd-hadd/src/HaddChar.java @@ -43,7 +43,7 @@ public class HaddChar { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddChar.halving_add_unsigned(char[], char[], char[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -93,7 +93,7 @@ public class HaddChar { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddChar.halving_add_also_unsigned(char[], char[], char[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -134,7 +134,7 @@ public class HaddChar { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddChar.rounding_halving_add_unsigned(char[], char[], char[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -186,7 +186,7 @@ public class HaddChar { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddChar.rounding_halving_add_also_unsigned(char[], char[], char[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -227,7 +227,7 @@ public class HaddChar { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddChar.halving_add_unsigned_constant(char[], char[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -276,7 +276,7 @@ public class HaddChar { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddChar.halving_add_also_unsigned_constant(char[], char[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd diff --git a/test/646-checker-simd-hadd/src/HaddOther.java b/test/646-checker-simd-hadd/src/HaddOther.java index 377ea9ab26..c8350c2b70 100644 --- a/test/646-checker-simd-hadd/src/HaddOther.java +++ b/test/646-checker-simd-hadd/src/HaddOther.java @@ -104,7 +104,7 @@ public class HaddOther { /// CHECK: VecHalvingAdd // /// CHECK-START-ARM64: void HaddOther.test_no_hadd_sum_cast_plus_const(short[], short[], short[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd diff --git a/test/646-checker-simd-hadd/src/HaddShort.java b/test/646-checker-simd-hadd/src/HaddShort.java index 9880a7a0da..bafaa29491 100644 --- a/test/646-checker-simd-hadd/src/HaddShort.java +++ b/test/646-checker-simd-hadd/src/HaddShort.java @@ -47,7 +47,7 @@ public class HaddShort { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddShort.halving_add_signed(short[], short[], short[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -88,7 +88,7 @@ public class HaddShort { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddShort.halving_add_signed_alt(short[], short[], short[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -139,7 +139,7 @@ public class HaddShort { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddShort.halving_add_unsigned(short[], short[], short[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -179,7 +179,7 @@ public class HaddShort { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddShort.rounding_halving_add_signed(short[], short[], short[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -217,7 +217,7 @@ public class HaddShort { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddShort.rounding_halving_add_signed_alt(short[], short[], short[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -259,7 +259,7 @@ public class HaddShort { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddShort.rounding_halving_add_signed_alt2(short[], short[], short[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -303,7 +303,7 @@ public class HaddShort { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddShort.rounding_halving_add_signed_alt3(short[], short[], short[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -356,7 +356,7 @@ public class HaddShort { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddShort.rounding_halving_add_unsigned(short[], short[], short[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -410,7 +410,7 @@ public class HaddShort { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddShort.rounding_halving_add_unsigned_alt(short[], short[], short[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -451,7 +451,7 @@ public class HaddShort { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddShort.halving_add_signed_constant(short[], short[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd @@ -501,7 +501,7 @@ public class HaddShort { /// CHECK-DAG: VecStore [{{l\d+}},{{i\d+}},<<HAdd>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void HaddShort.halving_add_unsigned_constant(short[], short[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // HalvingAdd idiom is not supported for SVE. /// CHECK-NOT: VecHalvingAdd diff --git a/test/655-checker-simd-arm-opt/src/Main.java b/test/655-checker-simd-arm-opt/src/Main.java index 5412aab6a1..cfd6f6a08a 100644 --- a/test/655-checker-simd-arm-opt/src/Main.java +++ b/test/655-checker-simd-arm-opt/src/Main.java @@ -38,7 +38,7 @@ public class Main { /// CHECK-DAG: <<D9:d\d+>> DoubleConstant 20 /// CHECK-DAG: <<D10:d\d+>> DoubleConstant 0 // - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: VecReplicateScalar [<<C1>>,{{j\d+}}] /// CHECK-DAG: VecReplicateScalar [<<C2>>,{{j\d+}}] @@ -104,7 +104,7 @@ public class Main { /// CHECK-DAG: VecStore loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: void Main.SVEIntermediateAddress(int) instruction_simplifier_arm64 (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' /// CHECK-DAG: <<IntAddr1:i\d+>> IntermediateAddress [{{l\d+}},{{i\d+}}] loop:<<Loop:B\d+>> outer_loop:none /// CHECK-DAG: VecLoad [<<IntAddr1>>,{{i\d+}},{{j\d+}}] loop:<<Loop>> outer_loop:none /// CHECK-DAG: VecAdd loop:<<Loop>> outer_loop:none @@ -113,7 +113,7 @@ public class Main { /// CHECK-FI: // /// CHECK-START-ARM64: void Main.SVEIntermediateAddress(int) GVN$after_arch (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' /// CHECK-DAG: <<IntAddr:i\d+>> IntermediateAddress [{{l\d+}},{{i\d+}}] loop:<<Loop:B\d+>> outer_loop:none /// CHECK-DAG: VecLoad [<<IntAddr>>,{{i\d+}},{{j\d+}}] loop:<<Loop>> outer_loop:none /// CHECK-DAG: VecAdd loop:<<Loop>> outer_loop:none diff --git a/test/656-checker-simd-opt/src/Main.java b/test/656-checker-simd-opt/src/Main.java index 9fc4536a4d..6b08d6352e 100644 --- a/test/656-checker-simd-opt/src/Main.java +++ b/test/656-checker-simd-opt/src/Main.java @@ -31,7 +31,7 @@ public class Main { /// CHECK-START-{X86_64,ARM64}: void Main.unroll(float[], float[]) loop_optimization (after) /// CHECK-DAG: <<Cons:f\d+>> FloatConstant 2.5 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Cons>>,{{j\d+}}] loop:none /// CHECK-NOT: VecReplicateScalar @@ -68,7 +68,7 @@ public class Main { /// CHECK-START-{X86_64,ARM64}: void Main.stencil(int[], int[], int) loop_optimization (after) /// CHECK-DAG: <<CP1:i\d+>> IntConstant 1 loop:none /// CHECK-DAG: <<CP2:i\d+>> IntConstant 2 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Phi:i\d+>> Phi loop:<<Loop:B\d+>> outer_loop:none /// CHECK-DAG: <<LoopP:j\d+>> VecPredWhile [<<Phi>>,{{i\d+}}] loop:<<Loop>> outer_loop:none @@ -115,7 +115,7 @@ public class Main { /// CHECK-DAG: <<TCSel:i\d+>> Select [<<C0>>,{{i\d+}},<<ArrCh>>] loop:none /// CHECK-DAG: <<PhiV:i\d+>> Phi [<<C0>>,{{i\d+}}] loop:<<LoopV:B\d+>> outer_loop:none // - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<LoopP:j\d+>> VecPredWhile [<<PhiV>>,{{i\d+}}] loop:<<LoopV>> outer_loop:none /// CHECK-DAG: <<Add1:i\d+>> Add [<<PhiV>>,<<CP1>>] loop:<<LoopV>> outer_loop:none @@ -172,7 +172,7 @@ public class Main { /// CHECK-START-{X86_64,ARM64}: void Main.stencilAddInt(int[], int[], int) loop_optimization (after) /// CHECK-DAG: <<CP1:i\d+>> IntConstant 1 loop:none /// CHECK-DAG: <<CP2:i\d+>> IntConstant 2 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Phi:i\d+>> Phi loop:<<Loop:B\d+>> outer_loop:none /// CHECK-DAG: <<LoopP:j\d+>> VecPredWhile [<<Phi>>,{{i\d+}}] loop:<<Loop>> outer_loop:none @@ -226,7 +226,7 @@ public class Main { /// CHECK-START-{X86_64,ARM64}: void Main.stencilSubInt(int[], int[], int) loop_optimization (after) /// CHECK-DAG: <<CP1:i\d+>> IntConstant 1 loop:none /// CHECK-DAG: <<CP2:i\d+>> IntConstant 2 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Phi:i\d+>> Phi loop:<<Loop:B\d+>> outer_loop:none /// CHECK-DAG: <<LoopP:j\d+>> VecPredWhile [<<Phi>>,{{i\d+}}] loop:<<Loop>> outer_loop:none @@ -278,7 +278,7 @@ public class Main { /// CHECK-DAG: <<L1:j\d+>> LongConstant 1 loop:none /// CHECK-DAG: <<I0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Get:j\d+>> ArrayGet [{{l\d+}},<<I0>>] loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Rep:d\d+>> VecReplicateScalar [<<Get>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Set:d\d+>> VecSetScalars [<<L1>>,{{j\d+}}] loop:none @@ -321,7 +321,7 @@ public class Main { /// CHECK-DAG: <<I1:i\d+>> IntConstant 1 loop:none /// CHECK-DAG: <<Get:j\d+>> ArrayGet [{{l\d+}},<<I0>>] loop:none /// CHECK-DAG: <<Cnv:i\d+>> TypeConversion [<<Get>>] loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Rep:d\d+>> VecReplicateScalar [<<Cnv>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Phi:i\d+>> Phi [<<I0>>,{{i\d+}}] loop:<<Loop:B\d+>> outer_loop:none @@ -360,7 +360,7 @@ public class Main { /// CHECK-DAG: <<I0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<L1:j\d+>> LongConstant 1 loop:none /// CHECK-DAG: <<Cnv:i\d+>> TypeConversion [<<L1>>] loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Rep:d\d+>> VecReplicateScalar [<<Cnv>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Phi:i\d+>> Phi [<<I0>>,{{i\d+}}] loop:<<Loop:B\d+>> outer_loop:none diff --git a/test/660-checker-simd-sad/src/SimdSadByte.java b/test/660-checker-simd-sad/src/SimdSadByte.java index 0591fd172b..f33783c571 100644 --- a/test/660-checker-simd-sad/src/SimdSadByte.java +++ b/test/660-checker-simd-sad/src/SimdSadByte.java @@ -101,7 +101,7 @@ public class SimdSadByte { // /// CHECK-START-ARM64: int SimdSadByte.sadByte2Int(byte[], byte[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -141,7 +141,7 @@ public class SimdSadByte { // /// CHECK-START-ARM64: int SimdSadByte.sadByte2IntAlt(byte[], byte[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -183,7 +183,7 @@ public class SimdSadByte { // /// CHECK-START-ARM64: int SimdSadByte.sadByte2IntAlt2(byte[], byte[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -232,7 +232,7 @@ public class SimdSadByte { /// CHECK-START-ARM64: long SimdSadByte.sadByte2Long(byte[], byte[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<ConsL:j\d+>> LongConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -278,7 +278,7 @@ public class SimdSadByte { /// CHECK-START-ARM64: long SimdSadByte.sadByte2LongAt1(byte[], byte[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<ConsL:j\d+>> LongConstant 1 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate diff --git a/test/660-checker-simd-sad/src/SimdSadInt.java b/test/660-checker-simd-sad/src/SimdSadInt.java index 74d87dee60..bc4a5d78de 100644 --- a/test/660-checker-simd-sad/src/SimdSadInt.java +++ b/test/660-checker-simd-sad/src/SimdSadInt.java @@ -41,7 +41,7 @@ public class SimdSadInt { /// CHECK-DAG: Add [<<I>>,<<Cons>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: int SimdSadInt.sadInt2Int(int[], int[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -116,7 +116,7 @@ public class SimdSadInt { /// CHECK-DAG: Add [<<I>>,<<Cons>>] loop:<<Loop>> outer_loop:none // /// CHECK-START-ARM64: int SimdSadInt.sadInt2IntAlt2(int[], int[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -163,7 +163,7 @@ public class SimdSadInt { /// CHECK-START-ARM64: long SimdSadInt.sadInt2Long(int[], int[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<ConsL:j\d+>> LongConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -209,7 +209,7 @@ public class SimdSadInt { /// CHECK-START-ARM64: long SimdSadInt.sadInt2LongAt1(int[], int[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<ConsL:j\d+>> LongConstant 1 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate diff --git a/test/660-checker-simd-sad/src/SimdSadLong.java b/test/660-checker-simd-sad/src/SimdSadLong.java index 149fad6803..3263ae3833 100644 --- a/test/660-checker-simd-sad/src/SimdSadLong.java +++ b/test/660-checker-simd-sad/src/SimdSadLong.java @@ -35,7 +35,7 @@ public class SimdSadLong { /// CHECK-START-ARM64: long SimdSadLong.sadLong2Long(long[], long[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<ConsL:j\d+>> LongConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -106,7 +106,7 @@ public class SimdSadLong { /// CHECK-START-ARM64: long SimdSadLong.sadLong2LongAlt2(long[], long[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<ConsL:j\d+>> LongConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -152,7 +152,7 @@ public class SimdSadLong { /// CHECK-START-ARM64: long SimdSadLong.sadLong2LongAt1(long[], long[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<ConsL:j\d+>> LongConstant 1 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate diff --git a/test/660-checker-simd-sad/src/SimdSadShort.java b/test/660-checker-simd-sad/src/SimdSadShort.java index 0f1d08b91e..bc4de467ea 100644 --- a/test/660-checker-simd-sad/src/SimdSadShort.java +++ b/test/660-checker-simd-sad/src/SimdSadShort.java @@ -72,7 +72,7 @@ public class SimdSadShort { // /// CHECK-START-ARM64: int SimdSadShort.sadShort2Int(short[], short[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -112,7 +112,7 @@ public class SimdSadShort { // /// CHECK-START-ARM64: int SimdSadShort.sadShort2IntAlt(short[], short[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -154,7 +154,7 @@ public class SimdSadShort { // /// CHECK-START-ARM64: int SimdSadShort.sadShort2IntAlt2(short[], short[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -200,7 +200,7 @@ public class SimdSadShort { /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Cons1:i\d+>> IntConstant 1 loop:none /// CHECK-DAG: <<Cons:i\d+>> IntConstant 7 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -241,7 +241,7 @@ public class SimdSadShort { /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Cons1:i\d+>> IntConstant 1 loop:none /// CHECK-DAG: <<Cons:i\d+>> IntConstant 7 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -282,7 +282,7 @@ public class SimdSadShort { /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Cons1:i\d+>> IntConstant 1 loop:none /// CHECK-DAG: <<Cons:i\d+>> IntConstant -7 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -325,7 +325,7 @@ public class SimdSadShort { /// CHECK-START-ARM64: long SimdSadShort.sadShort2Long(short[], short[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<ConsL:j\d+>> LongConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -371,7 +371,7 @@ public class SimdSadShort { /// CHECK-START-ARM64: long SimdSadShort.sadShort2LongAt1(short[], short[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<ConsL:j\d+>> LongConstant 1 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate diff --git a/test/660-checker-simd-sad/src/SimdSadShort2.java b/test/660-checker-simd-sad/src/SimdSadShort2.java index 9688f0e310..71e9fb0e5e 100644 --- a/test/660-checker-simd-sad/src/SimdSadShort2.java +++ b/test/660-checker-simd-sad/src/SimdSadShort2.java @@ -87,7 +87,7 @@ public class SimdSadShort2 { // /// CHECK-START-ARM64: int SimdSadShort2.sadCastChar2Int(char[], char[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -144,7 +144,7 @@ public class SimdSadShort2 { // /// CHECK-START-ARM64: int SimdSadShort2.sadCastChar2IntAlt(char[], char[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -203,7 +203,7 @@ public class SimdSadShort2 { // /// CHECK-START-ARM64: int SimdSadShort2.sadCastChar2IntAlt2(char[], char[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -271,7 +271,7 @@ public class SimdSadShort2 { /// CHECK-START-ARM64: long SimdSadShort2.sadCastChar2Long(char[], char[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<ConsL:j\d+>> LongConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -336,7 +336,7 @@ public class SimdSadShort2 { /// CHECK-START-ARM64: long SimdSadShort2.sadCastChar2LongAt1(char[], char[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<ConsL:j\d+>> LongConstant 1 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate diff --git a/test/660-checker-simd-sad/src/SimdSadShort3.java b/test/660-checker-simd-sad/src/SimdSadShort3.java index 0687d1e0f2..cc92f69632 100644 --- a/test/660-checker-simd-sad/src/SimdSadShort3.java +++ b/test/660-checker-simd-sad/src/SimdSadShort3.java @@ -36,7 +36,7 @@ public class SimdSadShort3 { /// CHECK-START-ARM64: int SimdSadShort3.sadShort2IntParamRight(short[], short) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Param:s\d+>> ParameterValue loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -76,7 +76,7 @@ public class SimdSadShort3 { /// CHECK-START-ARM64: int SimdSadShort3.sadShort2IntParamLeft(short[], short) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Param:s\d+>> ParameterValue loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -116,7 +116,7 @@ public class SimdSadShort3 { /// CHECK-START-ARM64: int SimdSadShort3.sadShort2IntConstRight(short[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<ConsI:i\d+>> IntConstant 32767 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -156,7 +156,7 @@ public class SimdSadShort3 { /// CHECK-START-ARM64: int SimdSadShort3.sadShort2IntConstLeft(short[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<ConsI:i\d+>> IntConstant 32767 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -196,7 +196,7 @@ public class SimdSadShort3 { /// CHECK-START-ARM64: int SimdSadShort3.sadShort2IntInvariantRight(short[], int) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Conv:s\d+>> TypeConversion [{{i\d+}}] loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -237,7 +237,7 @@ public class SimdSadShort3 { /// CHECK-START-ARM64: int SimdSadShort3.sadShort2IntInvariantLeft(short[], int) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Conv:s\d+>> TypeConversion [{{i\d+}}] loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -280,7 +280,7 @@ public class SimdSadShort3 { /// CHECK-START-ARM64: int SimdSadShort3.sadShort2IntCastExprRight(short[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<ConsI:i\d+>> IntConstant 110 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate @@ -324,7 +324,7 @@ public class SimdSadShort3 { /// CHECK-START-ARM64: int SimdSadShort3.sadShort2IntCastExprLeft(short[]) loop_optimization (after) /// CHECK-DAG: <<Cons0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<ConsI:i\d+>> IntConstant 110 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // SAD idiom is not supported for SVE. /// CHECK-NOT: VecSADAccumulate diff --git a/test/661-checker-simd-cf-loops/src/Main.java b/test/661-checker-simd-cf-loops/src/Main.java index 95c09490bb..aee6c6a4f4 100644 --- a/test/661-checker-simd-cf-loops/src/Main.java +++ b/test/661-checker-simd-cf-loops/src/Main.java @@ -45,7 +45,7 @@ public class Main { public static final float MAGIC_FLOAT_ADD_CONST = 99.0f; /// CHECK-START-ARM64: int Main.$compile$noinline$FullDiamond(int[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<C0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<C4:i\d+>> IntConstant 4 loop:none @@ -92,7 +92,7 @@ public class Main { // /// CHECK-START-ARM64: void Main.$compile$noinline$SimpleBoolean(boolean[], boolean[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-NOT: VecLoad // @@ -109,7 +109,7 @@ public class Main { } /// CHECK-START-ARM64: void Main.$compile$noinline$SimpleByte(byte[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: VecLoad // @@ -124,7 +124,7 @@ public class Main { } /// CHECK-START-ARM64: void Main.$compile$noinline$SimpleUByte(byte[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: VecLoad // @@ -138,7 +138,7 @@ public class Main { } /// CHECK-START-ARM64: void Main.$compile$noinline$SimpleShort(short[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: VecLoad // @@ -153,7 +153,7 @@ public class Main { } /// CHECK-START-ARM64: void Main.$compile$noinline$SimpleChar(char[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: VecLoad // @@ -168,7 +168,7 @@ public class Main { } /// CHECK-START-ARM64: void Main.$compile$noinline$SimpleInt(int[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: VecLoad // @@ -183,7 +183,7 @@ public class Main { } /// CHECK-START-ARM64: void Main.$compile$noinline$SimpleLong(long[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-NOT: VecLoad // @@ -200,7 +200,7 @@ public class Main { } /// CHECK-START-ARM64: void Main.$compile$noinline$SimpleFloat(float[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-NOT: VecLoad // @@ -217,7 +217,7 @@ public class Main { } /// CHECK-START-ARM64: void Main.$compile$noinline$SimpleDouble(double[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-NOT: VecLoad // @@ -238,7 +238,7 @@ public class Main { // /// CHECK-START-ARM64: void Main.$compile$noinline$ByteConv(byte[], byte[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: VecLoad // @@ -253,7 +253,7 @@ public class Main { } /// CHECK-START-ARM64: void Main.$compile$noinline$UByteAndWrongConst(byte[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-NOT: VecLoad // @@ -269,7 +269,7 @@ public class Main { } /// CHECK-START-ARM64: void Main.$compile$noinline$ByteNoHiBits(byte[], byte[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-NOT: VecLoad // @@ -290,7 +290,7 @@ public class Main { // /// CHECK-START-ARM64: void Main.$compile$noinline$SimpleBelow(int[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-NOT: VecLoad // @@ -311,7 +311,7 @@ public class Main { // /// CHECK-START-ARM64: void Main.$compile$noinline$Select(int[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-NOT: VecLoad // @@ -329,7 +329,7 @@ public class Main { } /// CHECK-START-ARM64: void Main.$compile$noinline$Phi(int[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-NOT: VecLoad // @@ -350,7 +350,7 @@ public class Main { // TODO: when Phis are supported, test dotprod and sad idioms. /// CHECK-START-ARM64: int Main.$compile$noinline$Reduction(int[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-NOT: VecLoad // @@ -369,7 +369,7 @@ public class Main { } /// CHECK-START-ARM64: int Main.$compile$noinline$ReductionBackEdge(int[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: VecLoad // @@ -395,7 +395,7 @@ public class Main { public static final int STENCIL_ARRAY_SIZE = 130; /// CHECK-START-ARM64: void Main.$compile$noinline$stencilAlike(int[], int[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-NOT: VecLoad // @@ -416,7 +416,7 @@ public class Main { } /// CHECK-START-ARM64: void Main.$compile$noinline$NotDiamondCf(int[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-NOT: VecLoad // @@ -435,7 +435,7 @@ public class Main { } /// CHECK-START-ARM64: void Main.$compile$noinline$BrokenInduction(int[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-NOT: VecLoad // diff --git a/test/661-checker-simd-reduc/src/Main.java b/test/661-checker-simd-reduc/src/Main.java index b480884621..e6a8a0cea6 100644 --- a/test/661-checker-simd-reduc/src/Main.java +++ b/test/661-checker-simd-reduc/src/Main.java @@ -73,7 +73,7 @@ public class Main { /// CHECK-DAG: <<Extr:i\d+>> VecExtractScalar [<<Red>>] loop:none /// CHECK-START-ARM64: int Main.reductionInt(int[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<TrueC:i\d+>> IntConstant 1 loop:none /// CHECK-DAG: <<Set:d\d+>> VecSetScalars [{{i\d+}},{{j\d+}}] loop:none @@ -102,7 +102,7 @@ public class Main { // Check that full 128-bit Q-Register are saved across SuspendCheck slow path. /// CHECK-START-ARM64: int Main.reductionInt(int[]) disassembly (after) /// CHECK: SuspendCheckSlowPathARM64 - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK: str z<<RegNo:\d+>>, /// CHECK: ldr z<<RegNo>>, @@ -157,7 +157,7 @@ public class Main { /// CHECK-EVAL: "<<Loop1>>" != "<<Loop2>>" // /// CHECK-START-ARM64: int Main.reductionIntChain() loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Set1:d\d+>> VecSetScalars [{{i\d+}},{{j\d+}}] loop:none /// CHECK-DAG: <<Phi1:d\d+>> Phi [<<Set1>>,{{d\d+}}] loop:<<Loop1:B\d+>> outer_loop:none @@ -234,7 +234,7 @@ public class Main { /// CHECK-DAG: <<Extr:i\d+>> VecExtractScalar [<<Red>>] loop:none // /// CHECK-START-ARM64: int Main.reductionIntToLoop(int[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Set:d\d+>> VecSetScalars [{{i\d+}},{{j\d+}}] loop:none /// CHECK-DAG: <<Phi:d\d+>> Phi [<<Set>>,{{d\d+}}] loop:<<Loop1:B\d+>> outer_loop:none @@ -280,7 +280,7 @@ public class Main { /// CHECK-DAG: Return [<<Phi2>>] loop:none // /// CHECK-START-ARM64: long Main.reductionLong(long[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Cons2:i\d+>> IntConstant loop:none /// CHECK-DAG: <<Set:d\d+>> VecSetScalars [{{j\d+}},{{j\d+}}] loop:none @@ -358,7 +358,7 @@ public class Main { /// CHECK-DAG: <<Extr:i\d+>> VecExtractScalar [<<Red>>] loop:none // /// CHECK-START-ARM64: int Main.reductionIntM1(int[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Set:d\d+>> VecSetScalars [{{i\d+}},{{j\d+}}] loop:none /// CHECK-DAG: <<Phi:d\d+>> Phi [<<Set>>,{{d\d+}}] loop:<<Loop:B\d+>> outer_loop:none @@ -401,7 +401,7 @@ public class Main { /// CHECK-DAG: Return [<<Phi2>>] loop:none // /// CHECK-START-ARM64: long Main.reductionLongM1(long[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Set:d\d+>> VecSetScalars [{{j\d+}},{{j\d+}}] loop:none /// CHECK-DAG: <<Phi:d\d+>> Phi [<<Set>>,{{d\d+}}] loop:<<Loop:B\d+>> outer_loop:none @@ -477,7 +477,7 @@ public class Main { /// CHECK-DAG: <<Extr:i\d+>> VecExtractScalar [<<Red>>] loop:none // /// CHECK-START-ARM64: int Main.reductionMinusInt(int[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Set:d\d+>> VecSetScalars [{{i\d+}},{{j\d+}}] loop:none /// CHECK-DAG: <<Phi:d\d+>> Phi [<<Set>>,{{d\d+}}] loop:<<Loop:B\d+>> outer_loop:none @@ -520,7 +520,7 @@ public class Main { /// CHECK-DAG: Return [<<Phi2>>] loop:none // /// CHECK-START-ARM64: long Main.reductionMinusLong(long[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Set:d\d+>> VecSetScalars [{{j\d+}},{{j\d+}}] loop:none /// CHECK-DAG: <<Phi:d\d+>> Phi [<<Set>>,{{d\d+}}] loop:<<Loop:B\d+>> outer_loop:none diff --git a/test/665-checker-simd-zero/src/Main.java b/test/665-checker-simd-zero/src/Main.java index 3960c40bcc..ed9935d6f6 100644 --- a/test/665-checker-simd-zero/src/Main.java +++ b/test/665-checker-simd-zero/src/Main.java @@ -26,7 +26,7 @@ public class Main { // /// CHECK-START-ARM64: void Main.zeroz(boolean[]) loop_optimization (after) /// CHECK-DAG: <<Zero:i\d+>> IntConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Zero>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Phi:i\d+>> Phi loop:<<Loop:B\d+>> outer_loop:none @@ -52,7 +52,7 @@ public class Main { // /// CHECK-START-ARM64: void Main.zerob(byte[]) loop_optimization (after) /// CHECK-DAG: <<Zero:i\d+>> IntConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Zero>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Phi:i\d+>> Phi loop:<<Loop:B\d+>> outer_loop:none @@ -78,7 +78,7 @@ public class Main { // /// CHECK-START-ARM64: void Main.zeroc(char[]) loop_optimization (after) /// CHECK-DAG: <<Zero:i\d+>> IntConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Zero>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Phi:i\d+>> Phi loop:<<Loop:B\d+>> outer_loop:none @@ -104,7 +104,7 @@ public class Main { // /// CHECK-START-ARM64: void Main.zeros(short[]) loop_optimization (after) /// CHECK-DAG: <<Zero:i\d+>> IntConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Zero>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Phi:i\d+>> Phi loop:<<Loop:B\d+>> outer_loop:none @@ -130,7 +130,7 @@ public class Main { // /// CHECK-START-ARM64: void Main.zeroi(int[]) loop_optimization (after) /// CHECK-DAG: <<Zero:i\d+>> IntConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Zero>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Phi:i\d+>> Phi loop:<<Loop:B\d+>> outer_loop:none @@ -156,7 +156,7 @@ public class Main { // /// CHECK-START-ARM64: void Main.zerol(long[]) loop_optimization (after) /// CHECK-DAG: <<Zero:j\d+>> LongConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Zero>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Phi:i\d+>> Phi loop:<<Loop:B\d+>> outer_loop:none @@ -182,7 +182,7 @@ public class Main { // /// CHECK-START-ARM64: void Main.zerof(float[]) loop_optimization (after) /// CHECK-DAG: <<Zero:f\d+>> FloatConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Zero>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Phi:i\d+>> Phi loop:<<Loop:B\d+>> outer_loop:none @@ -208,7 +208,7 @@ public class Main { // /// CHECK-START-ARM64: void Main.zerod(double[]) loop_optimization (after) /// CHECK-DAG: <<Zero:d\d+>> DoubleConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Zero>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Phi:i\d+>> Phi loop:<<Loop:B\d+>> outer_loop:none diff --git a/test/669-checker-break/src/Main.java b/test/669-checker-break/src/Main.java index 9f7b24ebbb..9117e1448a 100644 --- a/test/669-checker-break/src/Main.java +++ b/test/669-checker-break/src/Main.java @@ -51,7 +51,7 @@ public class Main { /// CHECK-DAG: <<Par:l\d+>> ParameterValue loop:none /// CHECK-DAG: <<One:i\d+>> IntConstant 1 loop:none /// CHECK-DAG: <<Nil:l\d+>> NullCheck [<<Par>>] loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Rep:d\d+>> VecReplicateScalar [<<One>>,{{j\d+}}] loop:none /// CHECK-DAG: <<LoopP:j\d+>> VecPredWhile loop:<<Loop:B\d+>> outer_loop:none @@ -152,7 +152,7 @@ public class Main { /// CHECK-DAG: <<Par:l\d+>> ParameterValue loop:none /// CHECK-DAG: <<One:i\d+>> IntConstant 1 loop:none /// CHECK-DAG: <<Three:i\d+>> IntConstant 3 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Rep:d\d+>> VecReplicateScalar [<<Three>>,{{j\d+}}] loop:none /// CHECK-DAG: <<LoopP:j\d+>> VecPredWhile loop:<<Loop:B\d+>> outer_loop:none @@ -284,7 +284,7 @@ public class Main { /// CHECK-START-ARM64: int Main.breakLoopReduction(int[]) loop_optimization (after) /// CHECK-DAG: <<Par:l\d+>> ParameterValue loop:none /// CHECK-DAG: <<Zero:i\d+>> IntConstant 0 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Exp:d\d+>> VecSetScalars [<<Zero>>,{{j\d+}}] loop:none /// CHECK-DAG: <<LoopP:j\d+>> VecPredWhile loop:<<Loop:B\d+>> outer_loop:none diff --git a/test/684-checker-simd-dotprod/src/other/TestByte.java b/test/684-checker-simd-dotprod/src/other/TestByte.java index a67b3e94ba..a3222c62df 100644 --- a/test/684-checker-simd-dotprod/src/other/TestByte.java +++ b/test/684-checker-simd-dotprod/src/other/TestByte.java @@ -37,7 +37,7 @@ public class TestByte { /// CHECK-START-ARM64: int other.TestByte.testDotProdSimple(byte[], byte[]) loop_optimization (after) /// CHECK-DAG: <<Const0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Const1:i\d+>> IntConstant 1 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Set:d\d+>> VecSetScalars [<<Const1>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Phi1:i\d+>> Phi [<<Const0>>,{{i\d+}}] loop:<<Loop:B\d+>> outer_loop:none @@ -70,7 +70,7 @@ public class TestByte { /// CHECK-START-ARM64: int other.TestByte.testDotProdSimple(byte[], byte[]) disassembly (after) /// CHECK: VecDotProd - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' /// CHECK: sdot z{{\d+}}.s, z{{\d+}}.b, z{{\d+}}.b /// CHECK-ELIF: hasIsaFeature("dotprod") /// CHECK-NEXT: sdot v{{\d+}}.4s, v{{\d+}}.16b, v{{\d+}}.16b @@ -105,7 +105,7 @@ public class TestByte { /// CHECK-START-ARM64: int other.TestByte.testDotProdComplex(byte[], byte[]) loop_optimization (after) /// CHECK-DAG: <<Const0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Const1:i\d+>> IntConstant 1 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Const1>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Set:d\d+>> VecSetScalars [<<Const1>>,{{j\d+}}] loop:none @@ -163,7 +163,7 @@ public class TestByte { /// CHECK-START-ARM64: int other.TestByte.testDotProdSimpleUnsigned(byte[], byte[]) loop_optimization (after) /// CHECK-DAG: <<Const0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Const1:i\d+>> IntConstant 1 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Set:d\d+>> VecSetScalars [<<Const1>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Phi1:i\d+>> Phi [<<Const0>>,{{i\d+}}] loop:<<Loop:B\d+>> outer_loop:none @@ -195,7 +195,7 @@ public class TestByte { /// CHECK-START-ARM64: int other.TestByte.testDotProdSimpleUnsigned(byte[], byte[]) disassembly (after) /// CHECK: VecDotProd - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' /// CHECK: udot z{{\d+}}.s, z{{\d+}}.b, z{{\d+}}.b /// CHECK-ELIF: hasIsaFeature("dotprod") /// CHECK-NEXT: udot v{{\d+}}.4s, v{{\d+}}.16b, v{{\d+}}.16b @@ -230,7 +230,7 @@ public class TestByte { /// CHECK-START-ARM64: int other.TestByte.testDotProdComplexUnsigned(byte[], byte[]) loop_optimization (after) /// CHECK-DAG: <<Const0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Const1:i\d+>> IntConstant 1 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Const1>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Set:d\d+>> VecSetScalars [<<Const1>>,{{j\d+}}] loop:none @@ -292,7 +292,7 @@ public class TestByte { /// CHECK-START-ARM64: int other.TestByte.testDotProdComplexUnsignedCastToSigned(byte[], byte[]) loop_optimization (after) /// CHECK-DAG: <<Const0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Const1:i\d+>> IntConstant 1 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Const1>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Set:d\d+>> VecSetScalars [<<Const1>>,{{j\d+}}] loop:none @@ -354,7 +354,7 @@ public class TestByte { /// CHECK-START-ARM64: int other.TestByte.testDotProdComplexSignedCastToUnsigned(byte[], byte[]) loop_optimization (after) /// CHECK-DAG: <<Const0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Const1:i\d+>> IntConstant 1 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Const1>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Set:d\d+>> VecSetScalars [<<Const1>>,{{j\d+}}] loop:none diff --git a/test/684-checker-simd-dotprod/src/other/TestCharShort.java b/test/684-checker-simd-dotprod/src/other/TestCharShort.java index cd076496c1..803365d63c 100644 --- a/test/684-checker-simd-dotprod/src/other/TestCharShort.java +++ b/test/684-checker-simd-dotprod/src/other/TestCharShort.java @@ -37,7 +37,7 @@ public class TestCharShort { /// CHECK-START-{ARM64}: int other.TestCharShort.testDotProdSimple(short[], short[]) loop_optimization (after) /// CHECK-DAG: <<Const0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Const1:i\d+>> IntConstant 1 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // 16-bit DotProd is not supported for SVE. /// CHECK-NOT: VecDotProd @@ -84,7 +84,7 @@ public class TestCharShort { /// CHECK-START-{ARM64}: int other.TestCharShort.testDotProdComplex(short[], short[]) loop_optimization (after) /// CHECK-DAG: <<Const0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Const1:i\d+>> IntConstant 1 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // 16-bit DotProd is not supported for SVE. /// CHECK-NOT: VecDotProd @@ -130,7 +130,7 @@ public class TestCharShort { /// CHECK-START-{ARM64}: int other.TestCharShort.testDotProdSimpleUnsigned(char[], char[]) loop_optimization (after) /// CHECK-DAG: <<Const0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Const1:i\d+>> IntConstant 1 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // 16-bit DotProd is not supported for SVE. /// CHECK-NOT: VecDotProd @@ -177,7 +177,7 @@ public class TestCharShort { /// CHECK-START-{ARM64}: int other.TestCharShort.testDotProdComplexUnsigned(char[], char[]) loop_optimization (after) /// CHECK-DAG: <<Const0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Const1:i\d+>> IntConstant 1 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // 16-bit DotProd is not supported for SVE. /// CHECK-NOT: VecDotProd @@ -227,7 +227,7 @@ public class TestCharShort { /// CHECK-START-{ARM64}: int other.TestCharShort.testDotProdComplexUnsignedCastToSigned(char[], char[]) loop_optimization (after) /// CHECK-DAG: <<Const0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Const1:i\d+>> IntConstant 1 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // 16-bit DotProd is not supported for SVE. /// CHECK-NOT: VecDotProd @@ -277,7 +277,7 @@ public class TestCharShort { /// CHECK-START-{ARM64}: int other.TestCharShort.testDotProdComplexSignedCastToUnsigned(short[], short[]) loop_optimization (after) /// CHECK-DAG: <<Const0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Const1:i\d+>> IntConstant 1 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // 16-bit DotProd is not supported for SVE. /// CHECK-NOT: VecDotProd @@ -310,7 +310,7 @@ public class TestCharShort { } /// CHECK-START-{ARM64}: int other.TestCharShort.testDotProdSignedToInt(short[], short[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // 16-bit DotProd is not supported for SVE. /// CHECK-NOT: VecDotProd @@ -330,7 +330,7 @@ public class TestCharShort { } /// CHECK-START-{ARM64}: int other.TestCharShort.testDotProdParamSigned(int, short[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // 16-bit DotProd is not supported for SVE. /// CHECK-NOT: VecDotProd @@ -350,7 +350,7 @@ public class TestCharShort { } /// CHECK-START-{ARM64}: int other.TestCharShort.testDotProdParamUnsigned(int, char[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // 16-bit DotProd is not supported for SVE. /// CHECK-NOT: VecDotProd @@ -381,7 +381,7 @@ public class TestCharShort { } /// CHECK-START-{ARM64}: int other.TestCharShort.testDotProdSignedToChar(short[], short[]) loop_optimization (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // 16-bit DotProd is not supported for SVE. /// CHECK-NOT: VecDotProd diff --git a/test/684-checker-simd-dotprod/src/other/TestVarious.java b/test/684-checker-simd-dotprod/src/other/TestVarious.java index ef03da1fbd..631e2c3800 100644 --- a/test/684-checker-simd-dotprod/src/other/TestVarious.java +++ b/test/684-checker-simd-dotprod/src/other/TestVarious.java @@ -36,7 +36,7 @@ public class TestVarious { /// CHECK-DAG: <<Const0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Const1:i\d+>> IntConstant 1 loop:none /// CHECK-DAG: <<Const89:i\d+>> IntConstant 89 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Set:d\d+>> VecSetScalars [<<Const1>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Const89>>,{{j\d+}}] loop:none @@ -89,7 +89,7 @@ public class TestVarious { /// CHECK-DAG: <<Const0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Const1:i\d+>> IntConstant 1 loop:none /// CHECK-DAG: <<Const89:i\d+>> IntConstant 89 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Set:d\d+>> VecSetScalars [<<Const1>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Const89>>,{{j\d+}}] loop:none @@ -149,7 +149,7 @@ public class TestVarious { /// CHECK-DAG: <<ConstL:i\d+>> IntConstant 129 loop:none /// CHECK-DAG: <<AddP:i\d+>> Add [<<Param>>,<<ConstL>>] loop:none /// CHECK-DAG: <<TypeCnv:b\d+>> TypeConversion [<<AddP>>] loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Set:d\d+>> VecSetScalars [<<Const1>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<TypeCnv>>,{{j\d+}}] loop:none @@ -236,7 +236,7 @@ public class TestVarious { /// CHECK-START-{ARM64}: int other.TestVarious.testDotProdInt32(int[], int[]) loop_optimization (after) /// CHECK-DAG: <<Const0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Const1:i\d+>> IntConstant 1 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Set:d\d+>> VecSetScalars [<<Const1>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Phi1:i\d+>> Phi [<<Const0>>,{{i\d+}}] loop:<<Loop:B\d+>> outer_loop:none @@ -294,7 +294,7 @@ public class TestVarious { /// CHECK-DAG: <<Const0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Const1:i\d+>> IntConstant 1 loop:none /// CHECK-DAG: <<Const2:i\d+>> IntConstant 2 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Set1:d\d+>> VecSetScalars [<<Const1>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Set2:d\d+>> VecSetScalars [<<Const2>>,{{j\d+}}] loop:none @@ -359,7 +359,7 @@ public class TestVarious { /// CHECK-DAG: <<Const1:i\d+>> IntConstant 1 loop:none /// CHECK-DAG: <<Const2:i\d+>> IntConstant 2 loop:none /// CHECK-DAG: <<Const42:i\d+>> IntConstant 42 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Const42>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Set1:d\d+>> VecSetScalars [<<Const1>>,{{j\d+}}] loop:none @@ -425,7 +425,7 @@ public class TestVarious { /// CHECK-DAG: <<Const0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Const1:i\d+>> IntConstant 1 loop:none /// CHECK-DAG: <<Const2:i\d+>> IntConstant 2 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <<Set1:d\d+>> VecSetScalars [<<Const1>>,{{j\d+}}] loop:none /// CHECK-DAG: <<Set2:d\d+>> VecSetScalars [<<Const2>>,{{j\d+}}] loop:none @@ -491,7 +491,7 @@ public class TestVarious { /// CHECK-DAG: <<Const0:i\d+>> IntConstant 0 loop:none /// CHECK-DAG: <<Const1:i\d+>> IntConstant 1 loop:none /// CHECK-DAG: <<Const2:i\d+>> IntConstant 2 loop:none - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // 16-bit DotProd is not supported for SVE. /// CHECK-NOT: VecDotProd |