diff options
| author | 2023-08-08 11:25:27 +0000 | |
|---|---|---|
| committer | 2023-08-08 17:07:55 +0000 | |
| commit | 973cc9325dcf47edd233db95a00b99c36e0c54e3 (patch) | |
| tree | 1f30800f39ae61d1ff7bd338d32031c6a5a65afe | |
| parent | 5e572cfdea135c8e7061d50b6f7e1c0a88065ca8 (diff) | |
riscv64: Clean up assembler tests.
Remove unnecessary indirection for registers in assembler
tests, including x86 and x86-64 tests.
Remove unnecessary `riscv64::` qualifications from riscv64
assembler tests.
Test: m test-art-host-gtest
Bug: 283082089
Change-Id: Ia3b85c9532e49ac6277d31304bd7cbcfb2f7c738
| -rw-r--r-- | compiler/utils/assembler_test.h | 151 | ||||
| -rw-r--r-- | compiler/utils/riscv64/assembler_riscv64_test.cc | 963 | ||||
| -rw-r--r-- | compiler/utils/x86/assembler_x86_test.cc | 116 | ||||
| -rw-r--r-- | compiler/utils/x86_64/assembler_x86_64_test.cc | 224 |
4 files changed, 679 insertions, 775 deletions
diff --git a/compiler/utils/assembler_test.h b/compiler/utils/assembler_test.h index c2e5064faf..72f48367a6 100644 --- a/compiler/utils/assembler_test.h +++ b/compiler/utils/assembler_test.h @@ -26,6 +26,7 @@ #include <fstream> #include <iterator> +#include "base/array_ref.h" #include "base/macros.h" #include "base/malloc_arena_pool.h" #include "assembler_test_base.h" @@ -200,8 +201,8 @@ class AssemblerTest : public AssemblerTestBase { template <typename Reg1, typename Reg2, typename ImmType> std::string RepeatTemplatedRegistersImmBits(void (Ass::*f)(Reg1, Reg2, ImmType), int imm_bits, - const std::vector<Reg1*> reg1_registers, - const std::vector<Reg2*> reg2_registers, + ArrayRef<const Reg1> reg1_registers, + ArrayRef<const Reg2> reg2_registers, std::string (AssemblerTest::*GetName1)(const Reg1&), std::string (AssemblerTest::*GetName2)(const Reg2&), const std::string& fmt, @@ -215,12 +216,12 @@ class AssemblerTest : public AssemblerTestBase { for (int64_t imm : imms) { ImmType new_imm = CreateImmediate(imm); if (f != nullptr) { - (assembler_.get()->*f)(*reg1, *reg2, new_imm * multiplier + bias); + (assembler_.get()->*f)(reg1, reg2, new_imm * multiplier + bias); } std::string base = fmt; - ReplaceReg(REG1_TOKEN, (this->*GetName1)(*reg1), &base); - ReplaceReg(REG2_TOKEN, (this->*GetName2)(*reg2), &base); + ReplaceReg(REG1_TOKEN, (this->*GetName1)(reg1), &base); + ReplaceReg(REG2_TOKEN, (this->*GetName2)(reg2), &base); ReplaceImm(imm, bias, multiplier, &base); str += base; @@ -234,9 +235,9 @@ class AssemblerTest : public AssemblerTestBase { template <typename Reg1, typename Reg2, typename Reg3, typename ImmType> std::string RepeatTemplatedRegistersImmBits(void (Ass::*f)(Reg1, Reg2, Reg3, ImmType), int imm_bits, - const std::vector<Reg1*> reg1_registers, - const std::vector<Reg2*> reg2_registers, - const std::vector<Reg3*> reg3_registers, + ArrayRef<const Reg1> reg1_registers, + ArrayRef<const Reg2> reg2_registers, + ArrayRef<const Reg3> reg3_registers, std::string (AssemblerTest::*GetName1)(const Reg1&), std::string (AssemblerTest::*GetName2)(const Reg2&), std::string (AssemblerTest::*GetName3)(const Reg3&), @@ -251,13 +252,13 @@ class AssemblerTest : public AssemblerTestBase { for (int64_t imm : imms) { ImmType new_imm = CreateImmediate(imm); if (f != nullptr) { - (assembler_.get()->*f)(*reg1, *reg2, *reg3, new_imm + bias); + (assembler_.get()->*f)(reg1, reg2, reg3, new_imm + bias); } std::string base = fmt; - ReplaceReg(REG1_TOKEN, (this->*GetName1)(*reg1), &base); - ReplaceReg(REG2_TOKEN, (this->*GetName2)(*reg2), &base); - ReplaceReg(REG3_TOKEN, (this->*GetName3)(*reg3), &base); + ReplaceReg(REG1_TOKEN, (this->*GetName1)(reg1), &base); + ReplaceReg(REG2_TOKEN, (this->*GetName2)(reg2), &base); + ReplaceReg(REG3_TOKEN, (this->*GetName3)(reg3), &base); ReplaceImm(imm, bias, /*multiplier=*/ 1, &base); str += base; @@ -271,8 +272,8 @@ class AssemblerTest : public AssemblerTestBase { template <typename ImmType, typename Reg1, typename Reg2> std::string RepeatTemplatedImmBitsRegisters(void (Ass::*f)(ImmType, Reg1, Reg2), - const std::vector<Reg1*> reg1_registers, - const std::vector<Reg2*> reg2_registers, + ArrayRef<const Reg1> reg1_registers, + ArrayRef<const Reg2> reg2_registers, std::string (AssemblerTest::*GetName1)(const Reg1&), std::string (AssemblerTest::*GetName2)(const Reg2&), int imm_bits, @@ -287,12 +288,12 @@ class AssemblerTest : public AssemblerTestBase { for (int64_t imm : imms) { ImmType new_imm = CreateImmediate(imm); if (f != nullptr) { - (assembler_.get()->*f)(new_imm, *reg1, *reg2); + (assembler_.get()->*f)(new_imm, reg1, reg2); } std::string base = fmt; - ReplaceReg(REG1_TOKEN, (this->*GetName1)(*reg1), &base); - ReplaceReg(REG2_TOKEN, (this->*GetName2)(*reg2), &base); + ReplaceReg(REG1_TOKEN, (this->*GetName1)(reg1), &base); + ReplaceReg(REG2_TOKEN, (this->*GetName2)(reg2), &base); ReplaceImm(imm, /*bias=*/ 0, /*multiplier=*/ 1, &base); str += base; @@ -306,7 +307,7 @@ class AssemblerTest : public AssemblerTestBase { template <typename RegType, typename ImmType> std::string RepeatTemplatedRegisterImmBits(void (Ass::*f)(RegType, ImmType), int imm_bits, - const std::vector<RegType*> registers, + ArrayRef<const RegType> registers, std::string (AssemblerTest::*GetName)(const RegType&), const std::string& fmt, int bias) { @@ -317,11 +318,11 @@ class AssemblerTest : public AssemblerTestBase { for (int64_t imm : imms) { ImmType new_imm = CreateImmediate(imm); if (f != nullptr) { - (assembler_.get()->*f)(*reg, new_imm + bias); + (assembler_.get()->*f)(reg, new_imm + bias); } std::string base = fmt; - ReplaceReg(REG_TOKEN, (this->*GetName)(*reg), &base); + ReplaceReg(REG_TOKEN, (this->*GetName)(reg), &base); ReplaceImm(imm, bias, /*multiplier=*/ 1, &base); str += base; @@ -336,7 +337,7 @@ class AssemblerTest : public AssemblerTestBase { void (Ass::*f)(RegType, ImmType), int imm_bits, int shift, - const std::vector<RegType*> registers, + ArrayRef<const RegType> registers, std::string (AssemblerTest::*GetName)(const RegType&), const std::string& fmt, int bias) { @@ -347,11 +348,11 @@ class AssemblerTest : public AssemblerTestBase { for (int64_t imm : imms) { ImmType new_imm = CreateImmediate(imm); if (f != nullptr) { - (assembler_.get()->*f)(*reg, new_imm + bias); + (assembler_.get()->*f)(reg, new_imm + bias); } std::string base = fmt; - ReplaceReg(REG_TOKEN, (this->*GetName)(*reg), &base); + ReplaceReg(REG_TOKEN, (this->*GetName)(reg), &base); ReplaceImm(imm, bias, /*multiplier=*/ 1, &base); str += base; @@ -390,8 +391,8 @@ class AssemblerTest : public AssemblerTestBase { void (Ass::*f)(Reg1, Reg2, ImmType), int imm_bits, int shift, - const std::vector<Reg1*> reg1_registers, - const std::vector<Reg2*> reg2_registers, + ArrayRef<const Reg1> reg1_registers, + ArrayRef<const Reg2> reg2_registers, std::string (AssemblerTest::*GetName1)(const Reg1&), std::string (AssemblerTest::*GetName2)(const Reg2&), const std::string& fmt, @@ -405,12 +406,12 @@ class AssemblerTest : public AssemblerTestBase { for (int64_t imm : imms) { ImmType new_imm = CreateImmediate(imm); if (f != nullptr) { - (assembler_.get()->*f)(*reg1, *reg2, new_imm * multiplier + bias); + (assembler_.get()->*f)(reg1, reg2, new_imm * multiplier + bias); } std::string base = fmt; - ReplaceReg(REG1_TOKEN, (this->*GetName1)(*reg1), &base); - ReplaceReg(REG2_TOKEN, (this->*GetName2)(*reg2), &base); + ReplaceReg(REG1_TOKEN, (this->*GetName1)(reg1), &base); + ReplaceReg(REG2_TOKEN, (this->*GetName2)(reg2), &base); ReplaceImm(imm, bias, multiplier, &base); str += base; @@ -786,18 +787,18 @@ class AssemblerTest : public AssemblerTestBase { // Returns a vector of registers used by any of the repeat methods // involving an "R" (e.g. RepeatR). - virtual std::vector<Reg*> GetRegisters() = 0; + virtual ArrayRef<const Reg> GetRegisters() = 0; // Returns a vector of fp-registers used by any of the repeat methods // involving an "F" (e.g. RepeatFF). - virtual std::vector<FPReg*> GetFPRegisters() { + virtual ArrayRef<const FPReg> GetFPRegisters() { UNIMPLEMENTED(FATAL) << "Architecture does not support floating-point registers"; UNREACHABLE(); } // Returns a vector of dedicated simd-registers used by any of the repeat // methods involving an "V" (e.g. RepeatVV). - virtual std::vector<VecReg*> GetVectorRegisters() { + virtual ArrayRef<const VecReg> GetVectorRegisters() { UNIMPLEMENTED(FATAL) << "Architecture does not support vector registers"; UNREACHABLE(); } @@ -1226,7 +1227,7 @@ class AssemblerTest : public AssemblerTestBase { template <typename RegType, typename AddrType> std::string RepeatTemplatedRegMem(void (Ass::*f)(RegType, const AddrType&), - const std::vector<RegType*> registers, + ArrayRef<const RegType> registers, const std::vector<AddrType> addresses, std::string (AssemblerTest::*GetRName)(const RegType&), std::string (AssemblerTest::*GetAName)(const AddrType&), @@ -1236,11 +1237,11 @@ class AssemblerTest : public AssemblerTestBase { for (auto reg : registers) { for (auto addr : addresses) { if (f != nullptr) { - (assembler_.get()->*f)(*reg, addr); + (assembler_.get()->*f)(reg, addr); } std::string base = fmt; - ReplaceReg(REG_TOKEN, (this->*GetRName)(*reg), &base); + ReplaceReg(REG_TOKEN, (this->*GetRName)(reg), &base); ReplaceAddr((this->*GetAName)(addr), &base); str += base; @@ -1253,7 +1254,7 @@ class AssemblerTest : public AssemblerTestBase { template <typename AddrType, typename RegType> std::string RepeatTemplatedMemReg(void (Ass::*f)(const AddrType&, RegType), const std::vector<AddrType> addresses, - const std::vector<RegType*> registers, + ArrayRef<const RegType> registers, std::string (AssemblerTest::*GetAName)(const AddrType&), std::string (AssemblerTest::*GetRName)(const RegType&), const std::string& fmt) { @@ -1262,12 +1263,12 @@ class AssemblerTest : public AssemblerTestBase { for (auto addr : addresses) { for (auto reg : registers) { if (f != nullptr) { - (assembler_.get()->*f)(addr, *reg); + (assembler_.get()->*f)(addr, reg); } std::string base = fmt; ReplaceAddr((this->*GetAName)(addr), &base); - ReplaceReg(REG_TOKEN, (this->*GetRName)(*reg), &base); + ReplaceReg(REG_TOKEN, (this->*GetRName)(reg), &base); str += base; str += "\n"; @@ -1282,17 +1283,17 @@ class AssemblerTest : public AssemblerTestBase { template <typename RegType> std::string RepeatTemplatedRegister(void (Ass::*f)(RegType), - const std::vector<RegType*> registers, + ArrayRef<const RegType> registers, std::string (AssemblerTest::*GetName)(const RegType&), const std::string& fmt) { std::string str; for (auto reg : registers) { if (f != nullptr) { - (assembler_.get()->*f)(*reg); + (assembler_.get()->*f)(reg); } std::string base = fmt; - ReplaceReg(REG_TOKEN, (this->*GetName)(*reg), &base); + ReplaceReg(REG_TOKEN, (this->*GetName)(reg), &base); str += base; str += "\n"; @@ -1302,8 +1303,8 @@ class AssemblerTest : public AssemblerTestBase { template <typename Reg1, typename Reg2> std::string RepeatTemplatedRegisters(void (Ass::*f)(Reg1, Reg2), - const std::vector<Reg1*> reg1_registers, - const std::vector<Reg2*> reg2_registers, + ArrayRef<const Reg1> reg1_registers, + ArrayRef<const Reg2> reg2_registers, std::string (AssemblerTest::*GetName1)(const Reg1&), std::string (AssemblerTest::*GetName2)(const Reg2&), const std::string& fmt, @@ -1315,19 +1316,19 @@ class AssemblerTest : public AssemblerTestBase { for (auto reg2 : reg2_registers) { // Check if this register pair is on the exception list. If so, skip it. if (except != nullptr) { - const auto& pair = std::make_pair(*reg1, *reg2); + const auto& pair = std::make_pair(reg1, reg2); if (std::find(except->begin(), except->end(), pair) != except->end()) { continue; } } if (f != nullptr) { - (assembler_.get()->*f)(*reg1, *reg2); + (assembler_.get()->*f)(reg1, reg2); } std::string base = fmt; - ReplaceReg(REG1_TOKEN, (this->*GetName1)(*reg1), &base); - ReplaceReg(REG2_TOKEN, (this->*GetName2)(*reg2), &base); + ReplaceReg(REG1_TOKEN, (this->*GetName1)(reg1), &base); + ReplaceReg(REG2_TOKEN, (this->*GetName2)(reg2), &base); str += base; str += "\n"; @@ -1338,8 +1339,8 @@ class AssemblerTest : public AssemblerTestBase { template <typename Reg1, typename Reg2> std::string RepeatTemplatedRegistersNoDupes(void (Ass::*f)(Reg1, Reg2), - const std::vector<Reg1*> reg1_registers, - const std::vector<Reg2*> reg2_registers, + ArrayRef<const Reg1> reg1_registers, + ArrayRef<const Reg2> reg2_registers, std::string (AssemblerTest::*GetName1)(const Reg1&), std::string (AssemblerTest::*GetName2)(const Reg2&), const std::string& fmt) { @@ -1350,12 +1351,12 @@ class AssemblerTest : public AssemblerTestBase { for (auto reg2 : reg2_registers) { if (reg1 == reg2) continue; if (f != nullptr) { - (assembler_.get()->*f)(*reg1, *reg2); + (assembler_.get()->*f)(reg1, reg2); } std::string base = fmt; - ReplaceReg(REG1_TOKEN, (this->*GetName1)(*reg1), &base); - ReplaceReg(REG2_TOKEN, (this->*GetName2)(*reg2), &base); + ReplaceReg(REG1_TOKEN, (this->*GetName1)(reg1), &base); + ReplaceReg(REG2_TOKEN, (this->*GetName2)(reg2), &base); str += base; str += "\n"; @@ -1366,9 +1367,9 @@ class AssemblerTest : public AssemblerTestBase { template <typename Reg1, typename Reg2, typename Reg3> std::string RepeatTemplatedRegisters(void (Ass::*f)(Reg1, Reg2, Reg3), - const std::vector<Reg1*> reg1_registers, - const std::vector<Reg2*> reg2_registers, - const std::vector<Reg3*> reg3_registers, + ArrayRef<const Reg1> reg1_registers, + ArrayRef<const Reg2> reg2_registers, + ArrayRef<const Reg3> reg3_registers, std::string (AssemblerTest::*GetName1)(const Reg1&), std::string (AssemblerTest::*GetName2)(const Reg2&), std::string (AssemblerTest::*GetName3)(const Reg3&), @@ -1378,13 +1379,13 @@ class AssemblerTest : public AssemblerTestBase { for (auto reg2 : reg2_registers) { for (auto reg3 : reg3_registers) { if (f != nullptr) { - (assembler_.get()->*f)(*reg1, *reg2, *reg3); + (assembler_.get()->*f)(reg1, reg2, reg3); } std::string base = fmt; - ReplaceReg(REG1_TOKEN, (this->*GetName1)(*reg1), &base); - ReplaceReg(REG2_TOKEN, (this->*GetName2)(*reg2), &base); - ReplaceReg(REG3_TOKEN, (this->*GetName3)(*reg3), &base); + ReplaceReg(REG1_TOKEN, (this->*GetName1)(reg1), &base); + ReplaceReg(REG2_TOKEN, (this->*GetName2)(reg2), &base); + ReplaceReg(REG3_TOKEN, (this->*GetName3)(reg3), &base); str += base; str += "\n"; @@ -1396,10 +1397,10 @@ class AssemblerTest : public AssemblerTestBase { template <typename Reg1, typename Reg2, typename Reg3, typename Reg4> std::string RepeatTemplatedRegisters(void (Ass::*f)(Reg1, Reg2, Reg3, Reg4), - const std::vector<Reg1*>& reg1_registers, - const std::vector<Reg2*>& reg2_registers, - const std::vector<Reg3*>& reg3_registers, - const std::vector<Reg4*>& reg4_registers, + ArrayRef<const Reg1> reg1_registers, + ArrayRef<const Reg2> reg2_registers, + ArrayRef<const Reg3> reg3_registers, + ArrayRef<const Reg4> reg4_registers, std::string (AssemblerTest::*GetName1)(const Reg1&), std::string (AssemblerTest::*GetName2)(const Reg2&), std::string (AssemblerTest::*GetName3)(const Reg3&), @@ -1411,14 +1412,14 @@ class AssemblerTest : public AssemblerTestBase { for (auto reg3 : reg3_registers) { for (auto reg4 : reg4_registers) { if (f != nullptr) { - (assembler_.get()->*f)(*reg1, *reg2, *reg3, *reg4); + (assembler_.get()->*f)(reg1, reg2, reg3, reg4); } std::string base = fmt; - ReplaceReg(REG1_TOKEN, (this->*GetName1)(*reg1), &base); - ReplaceReg(REG2_TOKEN, (this->*GetName2)(*reg2), &base); - ReplaceReg(REG3_TOKEN, (this->*GetName3)(*reg3), &base); - ReplaceReg(REG4_TOKEN, (this->*GetName4)(*reg4), &base); + ReplaceReg(REG1_TOKEN, (this->*GetName1)(reg1), &base); + ReplaceReg(REG2_TOKEN, (this->*GetName2)(reg2), &base); + ReplaceReg(REG3_TOKEN, (this->*GetName3)(reg3), &base); + ReplaceReg(REG4_TOKEN, (this->*GetName4)(reg4), &base); str += base; str += "\n"; @@ -1431,8 +1432,8 @@ class AssemblerTest : public AssemblerTestBase { template <typename Reg1, typename Reg2> std::string RepeatTemplatedRegistersImm(void (Ass::*f)(Reg1, Reg2, const Imm&), - const std::vector<Reg1*> reg1_registers, - const std::vector<Reg2*> reg2_registers, + ArrayRef<const Reg1> reg1_registers, + ArrayRef<const Reg2> reg2_registers, std::string (AssemblerTest::*GetName1)(const Reg1&), std::string (AssemblerTest::*GetName2)(const Reg2&), size_t imm_bytes, @@ -1446,12 +1447,12 @@ class AssemblerTest : public AssemblerTestBase { for (int64_t imm : imms) { Imm new_imm = CreateImmediate(imm); if (f != nullptr) { - (assembler_.get()->*f)(*reg1, *reg2, new_imm); + (assembler_.get()->*f)(reg1, reg2, new_imm); } std::string base = fmt; - ReplaceReg(REG1_TOKEN, (this->*GetName1)(*reg1), &base); - ReplaceReg(REG2_TOKEN, (this->*GetName2)(*reg2), &base); + ReplaceReg(REG1_TOKEN, (this->*GetName1)(reg1), &base); + ReplaceReg(REG2_TOKEN, (this->*GetName2)(reg2), &base); ReplaceImm(imm, /*bias=*/ 0, /*multiplier=*/ 1, &base); str += base; @@ -1551,7 +1552,7 @@ class AssemblerTest : public AssemblerTestBase { std::string RepeatRegisterImm(void (Ass::*f)(Reg, const Imm&), size_t imm_bytes, const std::string& fmt) { - const std::vector<Reg*> registers = GetRegisters(); + ArrayRef<const Reg> registers = GetRegisters(); std::string str; std::vector<int64_t> imms = CreateImmediateValues(imm_bytes); @@ -1561,11 +1562,11 @@ class AssemblerTest : public AssemblerTestBase { for (int64_t imm : imms) { Imm new_imm = CreateImmediate(imm); if (f != nullptr) { - (assembler_.get()->*f)(*reg, new_imm); + (assembler_.get()->*f)(reg, new_imm); } std::string base = fmt; - ReplaceReg(REG_TOKEN, GetRegName<kRegView>(*reg), &base); + ReplaceReg(REG_TOKEN, GetRegName<kRegView>(reg), &base); ReplaceImm(imm, /*bias=*/ 0, /*multiplier=*/ 1, &base); str += base; diff --git a/compiler/utils/riscv64/assembler_riscv64_test.cc b/compiler/utils/riscv64/assembler_riscv64_test.cc index edf541ebbf..b3ead59d94 100644 --- a/compiler/utils/riscv64/assembler_riscv64_test.cc +++ b/compiler/utils/riscv64/assembler_riscv64_test.cc @@ -29,150 +29,154 @@ namespace art HIDDEN { namespace riscv64 { struct RISCV64CpuRegisterCompare { - bool operator()(const riscv64::XRegister& a, const riscv64::XRegister& b) const { return a < b; } + bool operator()(const XRegister& a, const XRegister& b) const { return a < b; } }; -class AssemblerRISCV64Test : public AssemblerTest<riscv64::Riscv64Assembler, - riscv64::Riscv64Label, - riscv64::XRegister, - riscv64::FRegister, +class AssemblerRISCV64Test : public AssemblerTest<Riscv64Assembler, + Riscv64Label, + XRegister, + FRegister, int32_t> { public: - using Base = AssemblerTest<riscv64::Riscv64Assembler, - riscv64::Riscv64Label, - riscv64::XRegister, - riscv64::FRegister, + using Base = AssemblerTest<Riscv64Assembler, + Riscv64Label, + XRegister, + FRegister, int32_t>; AssemblerRISCV64Test() : instruction_set_features_(Riscv64InstructionSetFeatures::FromVariant("default", nullptr)) {} protected: - riscv64::Riscv64Assembler* CreateAssembler(ArenaAllocator* allocator) override { - return new (allocator) riscv64::Riscv64Assembler(allocator, instruction_set_features_.get()); + Riscv64Assembler* CreateAssembler(ArenaAllocator* allocator) override { + return new (allocator) Riscv64Assembler(allocator, instruction_set_features_.get()); } InstructionSet GetIsa() override { return InstructionSet::kRiscv64; } void SetUpHelpers() override { - if (registers_.size() == 0) { - registers_.push_back(new riscv64::XRegister(riscv64::Zero)); - registers_.push_back(new riscv64::XRegister(riscv64::RA)); - registers_.push_back(new riscv64::XRegister(riscv64::SP)); - registers_.push_back(new riscv64::XRegister(riscv64::GP)); - registers_.push_back(new riscv64::XRegister(riscv64::TP)); - registers_.push_back(new riscv64::XRegister(riscv64::T0)); - registers_.push_back(new riscv64::XRegister(riscv64::T1)); - registers_.push_back(new riscv64::XRegister(riscv64::T2)); - registers_.push_back(new riscv64::XRegister(riscv64::S0)); - registers_.push_back(new riscv64::XRegister(riscv64::S1)); - registers_.push_back(new riscv64::XRegister(riscv64::A0)); - registers_.push_back(new riscv64::XRegister(riscv64::A1)); - registers_.push_back(new riscv64::XRegister(riscv64::A2)); - registers_.push_back(new riscv64::XRegister(riscv64::A3)); - registers_.push_back(new riscv64::XRegister(riscv64::A4)); - registers_.push_back(new riscv64::XRegister(riscv64::A5)); - registers_.push_back(new riscv64::XRegister(riscv64::A6)); - registers_.push_back(new riscv64::XRegister(riscv64::A7)); - registers_.push_back(new riscv64::XRegister(riscv64::S2)); - registers_.push_back(new riscv64::XRegister(riscv64::S3)); - registers_.push_back(new riscv64::XRegister(riscv64::S4)); - registers_.push_back(new riscv64::XRegister(riscv64::S5)); - registers_.push_back(new riscv64::XRegister(riscv64::S6)); - registers_.push_back(new riscv64::XRegister(riscv64::S7)); - registers_.push_back(new riscv64::XRegister(riscv64::S8)); - registers_.push_back(new riscv64::XRegister(riscv64::S9)); - registers_.push_back(new riscv64::XRegister(riscv64::S10)); - registers_.push_back(new riscv64::XRegister(riscv64::S11)); - registers_.push_back(new riscv64::XRegister(riscv64::T3)); - registers_.push_back(new riscv64::XRegister(riscv64::T4)); - registers_.push_back(new riscv64::XRegister(riscv64::T5)); - registers_.push_back(new riscv64::XRegister(riscv64::T6)); - - secondary_register_names_.emplace(riscv64::XRegister(riscv64::Zero), "zero"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::RA), "ra"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::SP), "sp"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::GP), "gp"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::TP), "tp"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::T0), "t0"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::T1), "t1"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::T2), "t2"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::S0), "s0"); // s0/fp - secondary_register_names_.emplace(riscv64::XRegister(riscv64::S1), "s1"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::A0), "a0"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::A1), "a1"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::A2), "a2"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::A3), "a3"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::A4), "a4"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::A5), "a5"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::A6), "a6"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::A7), "a7"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::S2), "s2"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::S3), "s3"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::S4), "s4"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::S5), "s5"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::S6), "s6"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::S7), "s7"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::S8), "s8"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::S9), "s9"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::S10), "s10"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::S11), "s11"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::T3), "t3"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::T4), "t4"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::T5), "t5"); - secondary_register_names_.emplace(riscv64::XRegister(riscv64::T6), "t6"); - - fp_registers_.push_back(new riscv64::FRegister(riscv64::FT0)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FT1)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FT2)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FT3)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FT4)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FT5)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FT6)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FT7)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FS0)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FS1)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FA0)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FA1)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FA2)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FA3)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FA4)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FA5)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FA6)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FA7)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FS2)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FS3)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FS4)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FS5)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FS6)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FS7)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FS8)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FS9)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FS10)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FS11)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FT8)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FT9)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FT10)); - fp_registers_.push_back(new riscv64::FRegister(riscv64::FT11)); + if (secondary_register_names_.empty()) { + secondary_register_names_.emplace(Zero, "zero"); + secondary_register_names_.emplace(RA, "ra"); + secondary_register_names_.emplace(SP, "sp"); + secondary_register_names_.emplace(GP, "gp"); + secondary_register_names_.emplace(TP, "tp"); + secondary_register_names_.emplace(T0, "t0"); + secondary_register_names_.emplace(T1, "t1"); + secondary_register_names_.emplace(T2, "t2"); + secondary_register_names_.emplace(S0, "s0"); // s0/fp + secondary_register_names_.emplace(S1, "s1"); + secondary_register_names_.emplace(A0, "a0"); + secondary_register_names_.emplace(A1, "a1"); + secondary_register_names_.emplace(A2, "a2"); + secondary_register_names_.emplace(A3, "a3"); + secondary_register_names_.emplace(A4, "a4"); + secondary_register_names_.emplace(A5, "a5"); + secondary_register_names_.emplace(A6, "a6"); + secondary_register_names_.emplace(A7, "a7"); + secondary_register_names_.emplace(S2, "s2"); + secondary_register_names_.emplace(S3, "s3"); + secondary_register_names_.emplace(S4, "s4"); + secondary_register_names_.emplace(S5, "s5"); + secondary_register_names_.emplace(S6, "s6"); + secondary_register_names_.emplace(S7, "s7"); + secondary_register_names_.emplace(S8, "s8"); + secondary_register_names_.emplace(S9, "s9"); + secondary_register_names_.emplace(S10, "s10"); + secondary_register_names_.emplace(S11, "s11"); + secondary_register_names_.emplace(T3, "t3"); + secondary_register_names_.emplace(T4, "t4"); + secondary_register_names_.emplace(T5, "t5"); + secondary_register_names_.emplace(T6, "t6"); } } void TearDown() override { AssemblerTest::TearDown(); - STLDeleteElements(®isters_); - STLDeleteElements(&fp_registers_); } - std::vector<riscv64::Riscv64Label> GetAddresses() override { + std::vector<Riscv64Label> GetAddresses() override { UNIMPLEMENTED(FATAL) << "Feature not implemented yet"; UNREACHABLE(); } - std::vector<riscv64::XRegister*> GetRegisters() override { return registers_; } + ArrayRef<const XRegister> GetRegisters() override { + static constexpr XRegister kXRegisters[] = { + Zero, + RA, + SP, + GP, + TP, + T0, + T1, + T2, + S0, + S1, + A0, + A1, + A2, + A3, + A4, + A5, + A6, + A7, + S2, + S3, + S4, + S5, + S6, + S7, + S8, + S9, + S10, + S11, + T3, + T4, + T5, + T6, + }; + return ArrayRef<const XRegister>(kXRegisters); + } - std::vector<riscv64::FRegister*> GetFPRegisters() override { return fp_registers_; } + ArrayRef<const FRegister> GetFPRegisters() override { + static constexpr FRegister kFRegisters[] = { + FT0, + FT1, + FT2, + FT3, + FT4, + FT5, + FT6, + FT7, + FS0, + FS1, + FA0, + FA1, + FA2, + FA3, + FA4, + FA5, + FA6, + FA7, + FS2, + FS3, + FS4, + FS5, + FS6, + FS7, + FS8, + FS9, + FS10, + FS11, + FT8, + FT9, + FT10, + FT11, + }; + return ArrayRef<const FRegister>(kFRegisters); + } - std::string GetSecondaryRegisterName(const riscv64::XRegister& reg) override { + std::string GetSecondaryRegisterName(const XRegister& reg) override { CHECK(secondary_register_names_.find(reg) != secondary_register_names_.end()); return secondary_register_names_[reg]; } @@ -213,15 +217,15 @@ class AssemblerRISCV64Test : public AssemblerTest<riscv64::Riscv64Assembler, } // Test various registers with a few small values. // (Even Zero is an accepted register even if that does not really load the requested value.) - for (XRegister* reg : GetRegisters()) { + for (XRegister reg : GetRegisters()) { ScratchRegisterScope srs(GetAssembler()); - srs.ExcludeXRegister(*reg); - std::string rd = GetRegisterName(*reg); - emit_load_const(*reg, -1); + srs.ExcludeXRegister(reg); + std::string rd = GetRegisterName(reg); + emit_load_const(reg, -1); expected += "li " + rd + ", -1\n"; - emit_load_const(*reg, 0); + emit_load_const(reg, 0); expected += "li " + rd + ", 0\n"; - emit_load_const(*reg, 1); + emit_load_const(reg, 1); expected += "li " + rd + ", 1\n"; } // Test some significant values. Some may just repeat the tests above but other values @@ -530,9 +534,9 @@ class AssemblerRISCV64Test : public AssemblerTest<riscv64::Riscv64Assembler, PrintJalRd&& print_jalrd) { std::string expected; Riscv64Label label; - for (XRegister* reg : GetRegisters()) { - __ Jal(*reg, &label); - expected += print_jalrd(*reg, label_name + "f"); + for (XRegister reg : GetRegisters()) { + __ Jal(reg, &label); + expected += print_jalrd(reg, label_name + "f"); } expected += EmitNops(gap_size); __ Bind(&label); @@ -550,9 +554,9 @@ class AssemblerRISCV64Test : public AssemblerTest<riscv64::Riscv64Assembler, __ Bind(&label); expected += label_name + ":\n"; expected += EmitNops(gap_size); - for (XRegister* reg : GetRegisters()) { - __ Jal(*reg, &label); - expected += print_jalrd(*reg, label_name + "b"); + for (XRegister reg : GetRegisters()) { + __ Jal(reg, &label); + expected += print_jalrd(reg, label_name + "b"); } DriverStr(expected, test_name); } @@ -648,27 +652,27 @@ class AssemblerRISCV64Test : public AssemblerTest<riscv64::Riscv64Assembler, large_values.push_back(0xfff); std::string expected; - for (XRegister* rd : GetRegisters()) { - std::string rd_name = GetRegisterName(*rd); + for (XRegister rd : GetRegisters()) { + std::string rd_name = GetRegisterName(rd); std::string addi_rd = ART_FORMAT("addi{} {}, ", suffix, rd_name); std::string add_rd = ART_FORMAT("add{} {}, ", suffix, rd_name); - for (XRegister* rs1 : GetRegisters()) { + for (XRegister rs1 : GetRegisters()) { ScratchRegisterScope srs(GetAssembler()); - srs.ExcludeXRegister(*rs1); - srs.ExcludeXRegister(*rd); + srs.ExcludeXRegister(rs1); + srs.ExcludeXRegister(rd); - std::string rs1_name = GetRegisterName(*rs1); - std::string tmp_name = GetRegisterName((*rs1 != TMP) ? TMP : TMP2); + std::string rs1_name = GetRegisterName(rs1); + std::string tmp_name = GetRegisterName((rs1 != TMP) ? TMP : TMP2); std::string addi_tmp = ART_FORMAT("addi{} {}, ", suffix, tmp_name); for (int64_t imm : kImm12s) { - emit_op(*rd, *rs1, imm); + emit_op(rd, rs1, imm); expected += ART_FORMAT("{}{}, {}\n", addi_rd, rs1_name, std::to_string(imm)); } auto emit_simple_ops = [&](ArrayRef<const int64_t> imms, int64_t adjustment) { for (int64_t imm : imms) { - emit_op(*rd, *rs1, imm); + emit_op(rd, rs1, imm); expected += ART_FORMAT("{}{}, {}\n", addi_tmp, rs1_name, std::to_string(adjustment)); expected += ART_FORMAT("{}{}, {}\n", addi_rd, tmp_name, std::to_string(imm - adjustment)); @@ -678,7 +682,7 @@ class AssemblerRISCV64Test : public AssemblerTest<riscv64::Riscv64Assembler, emit_simple_ops(ArrayRef<const int64_t>(kSimpleNegativeValues), -0x800); for (int64_t imm : large_values) { - emit_op(*rd, *rs1, imm); + emit_op(rd, rs1, imm); expected += ART_FORMAT("li {}, {}\n", tmp_name, std::to_string(imm)); expected += ART_FORMAT("{}{}, {}\n", add_rd, rs1_name, tmp_name); } @@ -721,24 +725,24 @@ class AssemblerRISCV64Test : public AssemblerTest<riscv64::Riscv64Assembler, }; std::string expected; - for (XRegister* rs1 : GetRegisters()) { - XRegister tmp = get_temp(*rs1); + for (XRegister rs1 : GetRegisters()) { + XRegister tmp = get_temp(rs1); if (tmp == kNoXRegister) { continue; // Unsupported register combination. } std::string tmp_name = GetRegisterName(tmp); ScratchRegisterScope srs(GetAssembler()); - srs.ExcludeXRegister(*rs1); - std::string rs1_name = GetRegisterName(*rs1); + srs.ExcludeXRegister(rs1); + std::string rs1_name = GetRegisterName(rs1); for (int64_t imm : kImm12s) { - emit_op(*rs1, imm); + emit_op(rs1, imm); expected += ART_FORMAT("{}, {}({})\n", head, std::to_string(imm), rs1_name); } auto emit_simple_ops = [&](ArrayRef<const int64_t> imms, int64_t adjustment) { for (int64_t imm : imms) { - emit_op(*rs1, imm); + emit_op(rs1, imm); expected += ART_FORMAT("addi {}, {}, {}\n", tmp_name, rs1_name, std::to_string(adjustment)); expected += ART_FORMAT("{}, {}({})\n", head, std::to_string(imm - adjustment), tmp_name); @@ -751,7 +755,7 @@ class AssemblerRISCV64Test : public AssemblerTest<riscv64::Riscv64Assembler, emit_simple_ops(ArrayRef<const int64_t>(kSimpleNegativeOffsets), -0x800); for (int64_t imm : kSplitOffsets) { - emit_op(*rs1, imm); + emit_op(rs1, imm); uint32_t imm20 = ((imm >> 12) + ((imm >> 11) & 1)) & 0xfffff; int32_t small_offset = (imm & 0xfff) - ((imm & 0x800) << 1); expected += ART_FORMAT("lui {}, {}\n", tmp_name, std::to_string(imm20)); @@ -760,7 +764,7 @@ class AssemblerRISCV64Test : public AssemblerTest<riscv64::Riscv64Assembler, } for (int64_t imm : kSpecialOffsets) { - emit_op(*rs1, imm); + emit_op(rs1, imm); expected += ART_FORMAT("lui {}, 0x80000\n", tmp_name); expected += ART_FORMAT("addiw {}, {}, {}\n", tmp_name, tmp_name, std::to_string(imm - 0x80000000)); @@ -776,22 +780,22 @@ class AssemblerRISCV64Test : public AssemblerTest<riscv64::Riscv64Assembler, void (Riscv64Assembler::*fn)(XRegister, XRegister, int32_t), bool is_store) { std::string expected; - for (XRegister* rd : GetRegisters()) { + for (XRegister rd : GetRegisters()) { ScratchRegisterScope srs(GetAssembler()); - srs.ExcludeXRegister(*rd); + srs.ExcludeXRegister(rd); auto get_temp = [&](XRegister rs1) { if (is_store) { - return (rs1 != TMP && *rd != TMP) + return (rs1 != TMP && rd != TMP) ? TMP - : (rs1 != TMP2 && *rd != TMP2) ? TMP2 : kNoXRegister; + : (rs1 != TMP2 && rd != TMP2) ? TMP2 : kNoXRegister; } else { return rs1 != TMP ? TMP : TMP2; } }; expected += RepeatLoadStoreArbitraryOffset( - insn + " " + GetRegisterName(*rd), + insn + " " + GetRegisterName(rd), get_temp, - [&](XRegister rs1, int64_t offset) { (GetAssembler()->*fn)(*rd, rs1, offset); }); + [&](XRegister rs1, int64_t offset) { (GetAssembler()->*fn)(rd, rs1, offset); }); } DriverStr(expected, test_name); } @@ -800,11 +804,11 @@ class AssemblerRISCV64Test : public AssemblerTest<riscv64::Riscv64Assembler, const std::string& insn, void (Riscv64Assembler::*fn)(FRegister, XRegister, int32_t)) { std::string expected; - for (FRegister* rd : GetFPRegisters()) { + for (FRegister rd : GetFPRegisters()) { expected += RepeatLoadStoreArbitraryOffset( - insn + " " + GetFPRegName(*rd), + insn + " " + GetFPRegName(rd), [&](XRegister rs1) { return rs1 != TMP ? TMP : TMP2; }, - [&](XRegister rs1, int64_t offset) { (GetAssembler()->*fn)(*rd, rs1, offset); }); + [&](XRegister rs1, int64_t offset) { (GetAssembler()->*fn)(rd, rs1, offset); }); } DriverStr(expected, test_name); } @@ -819,14 +823,14 @@ class AssemblerRISCV64Test : public AssemblerTest<riscv64::Riscv64Assembler, "auipc " + rd_name + ", %pcrel_hi(" + label + "f)\n" + load + " " + rd_name + ", %pcrel_lo(1b)(" + rd_name + ")\n"; }; - for (XRegister* reg : GetRegisters()) { - if (*reg != Zero) { - __ Loadw(*reg, narrow_literal); - print_load("lw", *reg, "2"); - __ Loadwu(*reg, narrow_literal); - print_load("lwu", *reg, "2"); - __ Loadd(*reg, wide_literal); - print_load("ld", *reg, "3"); + for (XRegister reg : GetRegisters()) { + if (reg != Zero) { + __ Loadw(reg, narrow_literal); + print_load("lw", reg, "2"); + __ Loadwu(reg, narrow_literal); + print_load("lwu", reg, "2"); + __ Loadd(reg, wide_literal); + print_load("ld", reg, "3"); } } std::string tmp = GetRegisterName(TMP); @@ -836,11 +840,11 @@ class AssemblerRISCV64Test : public AssemblerTest<riscv64::Riscv64Assembler, "auipc " + tmp + ", %pcrel_hi(" + label + "f)\n" + load + " " + rd_name + ", %pcrel_lo(1b)(" + tmp + ")\n"; }; - for (FRegister* freg : GetFPRegisters()) { - __ FLoadw(*freg, narrow_literal); - print_fp_load("flw", *freg, "2"); - __ FLoadd(*freg, wide_literal); - print_fp_load("fld", *freg, "3"); + for (FRegister freg : GetFPRegisters()) { + __ FLoadw(freg, narrow_literal); + print_fp_load("flw", freg, "2"); + __ FLoadd(freg, wide_literal); + print_fp_load("fld", freg, "3"); } // All literal loads above emit 8 bytes of code. The narrow literal shall emit 4 bytes of code. // If we do not add another instruction, we shall end up with padding before the long literal. @@ -858,18 +862,18 @@ class AssemblerRISCV64Test : public AssemblerTest<riscv64::Riscv64Assembler, const std::string& fmt) { CHECK(f != nullptr); std::string str; - for (FRegister* reg1 : GetFPRegisters()) { - for (FRegister* reg2 : GetFPRegisters()) { - for (FRegister* reg3 : GetFPRegisters()) { - for (FRegister* reg4 : GetFPRegisters()) { + for (FRegister reg1 : GetFPRegisters()) { + for (FRegister reg2 : GetFPRegisters()) { + for (FRegister reg3 : GetFPRegisters()) { + for (FRegister reg4 : GetFPRegisters()) { for (FPRoundingMode rm : kRoundingModes) { - (GetAssembler()->*f)(*reg1, *reg2, *reg3, *reg4, rm); + (GetAssembler()->*f)(reg1, reg2, reg3, reg4, rm); std::string base = fmt; - ReplaceReg(REG1_TOKEN, GetFPRegName(*reg1), &base); - ReplaceReg(REG2_TOKEN, GetFPRegName(*reg2), &base); - ReplaceReg(REG3_TOKEN, GetFPRegName(*reg3), &base); - ReplaceReg(REG4_TOKEN, GetFPRegName(*reg4), &base); + ReplaceReg(REG1_TOKEN, GetFPRegName(reg1), &base); + ReplaceReg(REG2_TOKEN, GetFPRegName(reg2), &base); + ReplaceReg(REG3_TOKEN, GetFPRegName(reg3), &base); + ReplaceReg(REG4_TOKEN, GetFPRegName(reg4), &base); ReplaceRoundingMode(rm, &base); str += base; str += "\n"; @@ -886,16 +890,16 @@ class AssemblerRISCV64Test : public AssemblerTest<riscv64::Riscv64Assembler, const std::string& fmt) { CHECK(f != nullptr); std::string str; - for (FRegister* reg1 : GetFPRegisters()) { - for (FRegister* reg2 : GetFPRegisters()) { - for (FRegister* reg3 : GetFPRegisters()) { + for (FRegister reg1 : GetFPRegisters()) { + for (FRegister reg2 : GetFPRegisters()) { + for (FRegister reg3 : GetFPRegisters()) { for (FPRoundingMode rm : kRoundingModes) { - (GetAssembler()->*f)(*reg1, *reg2, *reg3, rm); + (GetAssembler()->*f)(reg1, reg2, reg3, rm); std::string base = fmt; - ReplaceReg(REG1_TOKEN, GetFPRegName(*reg1), &base); - ReplaceReg(REG2_TOKEN, GetFPRegName(*reg2), &base); - ReplaceReg(REG3_TOKEN, GetFPRegName(*reg3), &base); + ReplaceReg(REG1_TOKEN, GetFPRegName(reg1), &base); + ReplaceReg(REG2_TOKEN, GetFPRegName(reg2), &base); + ReplaceReg(REG3_TOKEN, GetFPRegName(reg3), &base); ReplaceRoundingMode(rm, &base); str += base; str += "\n"; @@ -909,21 +913,21 @@ class AssemblerRISCV64Test : public AssemblerTest<riscv64::Riscv64Assembler, template <typename Reg1, typename Reg2> std::string RepeatTemplatedRegistersRoundingMode( void (Riscv64Assembler::*f)(Reg1, Reg2, FPRoundingMode), - const std::vector<Reg1*>& reg1_registers, - const std::vector<Reg2*>& reg2_registers, + ArrayRef<const Reg1> reg1_registers, + ArrayRef<const Reg2> reg2_registers, std::string (Base::*GetName1)(const Reg1&), std::string (Base::*GetName2)(const Reg2&), const std::string& fmt) { CHECK(f != nullptr); std::string str; - for (Reg1* reg1 : reg1_registers) { - for (Reg2* reg2 : reg2_registers) { + for (Reg1 reg1 : reg1_registers) { + for (Reg2 reg2 : reg2_registers) { for (FPRoundingMode rm : kRoundingModes) { - (GetAssembler()->*f)(*reg1, *reg2, rm); + (GetAssembler()->*f)(reg1, reg2, rm); std::string base = fmt; - ReplaceReg(REG1_TOKEN, (this->*GetName1)(*reg1), &base); - ReplaceReg(REG2_TOKEN, (this->*GetName2)(*reg2), &base); + ReplaceReg(REG1_TOKEN, (this->*GetName1)(reg1), &base); + ReplaceReg(REG2_TOKEN, (this->*GetName2)(reg2), &base); ReplaceRoundingMode(rm, &base); str += base; str += "\n"; @@ -971,14 +975,14 @@ class AssemblerRISCV64Test : public AssemblerTest<riscv64::Riscv64Assembler, CHECK(f != nullptr); std::vector<int64_t> imms = CreateImmediateValuesBits(2, /*as_uint=*/ true); std::string str; - for (XRegister* reg1 : GetRegisters()) { - for (XRegister* reg2 : GetRegisters()) { + for (XRegister reg1 : GetRegisters()) { + for (XRegister reg2 : GetRegisters()) { for (int64_t imm : imms) { - (GetAssembler()->*f)(*reg1, *reg2, dchecked_integral_cast<uint32_t>(imm)); + (GetAssembler()->*f)(reg1, reg2, dchecked_integral_cast<uint32_t>(imm)); std::string base = fmt; - ReplaceReg(REG1_TOKEN, GetRegisterName(*reg1), &base); - ReplaceReg(REG2_TOKEN, GetRegisterName(*reg2), &base); + ReplaceReg(REG1_TOKEN, GetRegisterName(reg1), &base); + ReplaceReg(REG2_TOKEN, GetRegisterName(reg2), &base); ReplaceAqRl(imm, &base); str += base; str += "\n"; @@ -993,16 +997,16 @@ class AssemblerRISCV64Test : public AssemblerTest<riscv64::Riscv64Assembler, CHECK(f != nullptr); std::vector<int64_t> imms = CreateImmediateValuesBits(2, /*as_uint=*/ true); std::string str; - for (XRegister* reg1 : GetRegisters()) { - for (XRegister* reg2 : GetRegisters()) { - for (XRegister* reg3 : GetRegisters()) { + for (XRegister reg1 : GetRegisters()) { + for (XRegister reg2 : GetRegisters()) { + for (XRegister reg3 : GetRegisters()) { for (int64_t imm : imms) { - (GetAssembler()->*f)(*reg1, *reg2, *reg3, dchecked_integral_cast<uint32_t>(imm)); + (GetAssembler()->*f)(reg1, reg2, reg3, dchecked_integral_cast<uint32_t>(imm)); std::string base = fmt; - ReplaceReg(REG1_TOKEN, GetRegisterName(*reg1), &base); - ReplaceReg(REG2_TOKEN, GetRegisterName(*reg2), &base); - ReplaceReg(REG3_TOKEN, GetRegisterName(*reg3), &base); + ReplaceReg(REG1_TOKEN, GetRegisterName(reg1), &base); + ReplaceReg(REG2_TOKEN, GetRegisterName(reg2), &base); + ReplaceReg(REG3_TOKEN, GetRegisterName(reg3), &base); ReplaceAqRl(imm, &base); str += base; str += "\n"; @@ -1018,15 +1022,15 @@ class AssemblerRISCV64Test : public AssemblerTest<riscv64::Riscv64Assembler, CHECK(f != nullptr); std::vector<int64_t> csrs = CreateImmediateValuesBits(12, /*as_uint=*/ true); std::string str; - for (XRegister* reg1 : GetRegisters()) { + for (XRegister reg1 : GetRegisters()) { for (int64_t csr : csrs) { - for (XRegister* reg2 : GetRegisters()) { - (GetAssembler()->*f)(*reg1, dchecked_integral_cast<uint32_t>(csr), *reg2); + for (XRegister reg2 : GetRegisters()) { + (GetAssembler()->*f)(reg1, dchecked_integral_cast<uint32_t>(csr), reg2); std::string base = fmt; - ReplaceReg(REG1_TOKEN, GetRegisterName(*reg1), &base); + ReplaceReg(REG1_TOKEN, GetRegisterName(reg1), &base); ReplaceCsrrImm(CSR_TOKEN, csr, &base); - ReplaceReg(REG2_TOKEN, GetRegisterName(*reg2), &base); + ReplaceReg(REG2_TOKEN, GetRegisterName(reg2), &base); str += base; str += "\n"; } @@ -1041,14 +1045,14 @@ class AssemblerRISCV64Test : public AssemblerTest<riscv64::Riscv64Assembler, std::vector<int64_t> csrs = CreateImmediateValuesBits(12, /*as_uint=*/ true); std::vector<int64_t> uimms = CreateImmediateValuesBits(2, /*as_uint=*/ true); std::string str; - for (XRegister* reg : GetRegisters()) { + for (XRegister reg : GetRegisters()) { for (int64_t csr : csrs) { for (int64_t uimm : uimms) { (GetAssembler()->*f)( - *reg, dchecked_integral_cast<uint32_t>(csr), dchecked_integral_cast<uint32_t>(uimm)); + reg, dchecked_integral_cast<uint32_t>(csr), dchecked_integral_cast<uint32_t>(uimm)); std::string base = fmt; - ReplaceReg(REG_TOKEN, GetRegisterName(*reg), &base); + ReplaceReg(REG_TOKEN, GetRegisterName(reg), &base); ReplaceCsrrImm(CSR_TOKEN, csr, &base); ReplaceCsrrImm(UIMM_TOKEN, uimm, &base); str += base; @@ -1065,12 +1069,12 @@ class AssemblerRISCV64Test : public AssemblerTest<riscv64::Riscv64Assembler, EmitCssrX&& emit_csrrx) { std::vector<int64_t> csrs = CreateImmediateValuesBits(12, /*as_uint=*/ true); std::string expected; - for (XRegister* reg : GetRegisters()) { + for (XRegister reg : GetRegisters()) { for (int64_t csr : csrs) { - emit_csrrx(dchecked_integral_cast<uint32_t>(csr), *reg); + emit_csrrx(dchecked_integral_cast<uint32_t>(csr), reg); std::string base = fmt; - ReplaceReg(REG_TOKEN, GetRegisterName(*reg), &base); + ReplaceReg(REG_TOKEN, GetRegisterName(reg), &base); ReplaceCsrrImm(CSR_TOKEN, csr, &base); expected += base; expected += "\n"; @@ -1183,10 +1187,7 @@ class AssemblerRISCV64Test : public AssemblerTest<riscv64::Riscv64Assembler, } } - std::vector<riscv64::XRegister*> registers_; - std::map<riscv64::XRegister, std::string, RISCV64CpuRegisterCompare> secondary_register_names_; - - std::vector<riscv64::FRegister*> fp_registers_; + std::map<XRegister, std::string, RISCV64CpuRegisterCompare> secondary_register_names_; std::unique_ptr<const Riscv64InstructionSetFeatures> instruction_set_features_; }; @@ -1194,223 +1195,207 @@ class AssemblerRISCV64Test : public AssemblerTest<riscv64::Riscv64Assembler, TEST_F(AssemblerRISCV64Test, Toolchain) { EXPECT_TRUE(CheckTools()); } TEST_F(AssemblerRISCV64Test, Lui) { - DriverStr(RepeatRIb(&riscv64::Riscv64Assembler::Lui, 20, "lui {reg}, {imm}"), "Lui"); + DriverStr(RepeatRIb(&Riscv64Assembler::Lui, 20, "lui {reg}, {imm}"), "Lui"); } TEST_F(AssemblerRISCV64Test, Auipc) { - DriverStr(RepeatRIb(&riscv64::Riscv64Assembler::Auipc, 20, "auipc {reg}, {imm}"), "Auipc"); + DriverStr(RepeatRIb(&Riscv64Assembler::Auipc, 20, "auipc {reg}, {imm}"), "Auipc"); } TEST_F(AssemblerRISCV64Test, Jal) { // TODO(riscv64): Change "-19, 2" to "-20, 1" for "C" Standard Extension. - DriverStr(RepeatRIbS(&riscv64::Riscv64Assembler::Jal, -19, 2, "jal {reg}, {imm}\n"), - "Jal"); + DriverStr(RepeatRIbS(&Riscv64Assembler::Jal, -19, 2, "jal {reg}, {imm}\n"), "Jal"); } TEST_F(AssemblerRISCV64Test, Jalr) { // TODO(riscv64): Change "-11, 2" to "-12, 1" for "C" Standard Extension. - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Jalr, -12, "jalr {reg1}, {reg2}, {imm}\n"), - "Jalr"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Jalr, -12, "jalr {reg1}, {reg2}, {imm}\n"), "Jalr"); } TEST_F(AssemblerRISCV64Test, Beq) { // TODO(riscv64): Change "-11, 2" to "-12, 1" for "C" Standard Extension. - DriverStr(RepeatRRIbS(&riscv64::Riscv64Assembler::Beq, -11, 2, "beq {reg1}, {reg2}, {imm}\n"), - "Beq"); + DriverStr(RepeatRRIbS(&Riscv64Assembler::Beq, -11, 2, "beq {reg1}, {reg2}, {imm}\n"), "Beq"); } TEST_F(AssemblerRISCV64Test, Bne) { // TODO(riscv64): Change "-11, 2" to "-12, 1" for "C" Standard Extension. - DriverStr(RepeatRRIbS(&riscv64::Riscv64Assembler::Bne, -11, 2, "bne {reg1}, {reg2}, {imm}\n"), - "Bne"); + DriverStr(RepeatRRIbS(&Riscv64Assembler::Bne, -11, 2, "bne {reg1}, {reg2}, {imm}\n"), "Bne"); } TEST_F(AssemblerRISCV64Test, Blt) { // TODO(riscv64): Change "-11, 2" to "-12, 1" for "C" Standard Extension. - DriverStr(RepeatRRIbS(&riscv64::Riscv64Assembler::Blt, -11, 2, "blt {reg1}, {reg2}, {imm}\n"), - "Blt"); + DriverStr(RepeatRRIbS(&Riscv64Assembler::Blt, -11, 2, "blt {reg1}, {reg2}, {imm}\n"), "Blt"); } TEST_F(AssemblerRISCV64Test, Bge) { // TODO(riscv64): Change "-11, 2" to "-12, 1" for "C" Standard Extension. - DriverStr(RepeatRRIbS(&riscv64::Riscv64Assembler::Bge, -11, 2, "bge {reg1}, {reg2}, {imm}\n"), - "Bge"); + DriverStr(RepeatRRIbS(&Riscv64Assembler::Bge, -11, 2, "bge {reg1}, {reg2}, {imm}\n"), "Bge"); } TEST_F(AssemblerRISCV64Test, Bltu) { // TODO(riscv64): Change "-11, 2" to "-12, 1" for "C" Standard Extension. - DriverStr(RepeatRRIbS(&riscv64::Riscv64Assembler::Bltu, -11, 2, "bltu {reg1}, {reg2}, {imm}\n"), - "Bltu"); + DriverStr(RepeatRRIbS(&Riscv64Assembler::Bltu, -11, 2, "bltu {reg1}, {reg2}, {imm}\n"), "Bltu"); } TEST_F(AssemblerRISCV64Test, Bgeu) { // TODO(riscv64): Change "-11, 2" to "-12, 1" for "C" Standard Extension. - DriverStr(RepeatRRIbS(&riscv64::Riscv64Assembler::Bgeu, -11, 2, "bgeu {reg1}, {reg2}, {imm}\n"), - "Bgeu"); + DriverStr(RepeatRRIbS(&Riscv64Assembler::Bgeu, -11, 2, "bgeu {reg1}, {reg2}, {imm}\n"), "Bgeu"); } TEST_F(AssemblerRISCV64Test, Lb) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Lb, -12, "lb {reg1}, {imm}({reg2})"), "Lb"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Lb, -12, "lb {reg1}, {imm}({reg2})"), "Lb"); } TEST_F(AssemblerRISCV64Test, Lh) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Lh, -12, "lh {reg1}, {imm}({reg2})"), "Lh"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Lh, -12, "lh {reg1}, {imm}({reg2})"), "Lh"); } TEST_F(AssemblerRISCV64Test, Lw) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Lw, -12, "lw {reg1}, {imm}({reg2})"), "Lw"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Lw, -12, "lw {reg1}, {imm}({reg2})"), "Lw"); } TEST_F(AssemblerRISCV64Test, Ld) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Ld, -12, "ld {reg1}, {imm}({reg2})"), "Ld"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Ld, -12, "ld {reg1}, {imm}({reg2})"), "Ld"); } TEST_F(AssemblerRISCV64Test, Lbu) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Lbu, -12, "lbu {reg1}, {imm}({reg2})"), "Lbu"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Lbu, -12, "lbu {reg1}, {imm}({reg2})"), "Lbu"); } TEST_F(AssemblerRISCV64Test, Lhu) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Lhu, -12, "lhu {reg1}, {imm}({reg2})"), "Lhu"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Lhu, -12, "lhu {reg1}, {imm}({reg2})"), "Lhu"); } TEST_F(AssemblerRISCV64Test, Lwu) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Lwu, -12, "lwu {reg1}, {imm}({reg2})"), "Lwu"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Lwu, -12, "lwu {reg1}, {imm}({reg2})"), "Lwu"); } TEST_F(AssemblerRISCV64Test, Sb) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Sb, -12, "sb {reg1}, {imm}({reg2})"), "Sb"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Sb, -12, "sb {reg1}, {imm}({reg2})"), "Sb"); } TEST_F(AssemblerRISCV64Test, Sh) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Sh, -12, "sh {reg1}, {imm}({reg2})"), "Sh"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Sh, -12, "sh {reg1}, {imm}({reg2})"), "Sh"); } TEST_F(AssemblerRISCV64Test, Sw) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Sw, -12, "sw {reg1}, {imm}({reg2})"), "Sw"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Sw, -12, "sw {reg1}, {imm}({reg2})"), "Sw"); } TEST_F(AssemblerRISCV64Test, Sd) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Sd, -12, "sd {reg1}, {imm}({reg2})"), "Sd"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Sd, -12, "sd {reg1}, {imm}({reg2})"), "Sd"); } TEST_F(AssemblerRISCV64Test, Addi) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Addi, -12, "addi {reg1}, {reg2}, {imm}"), - "Addi"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Addi, -12, "addi {reg1}, {reg2}, {imm}"), "Addi"); } TEST_F(AssemblerRISCV64Test, Slti) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Slti, -12, "slti {reg1}, {reg2}, {imm}"), - "Slti"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Slti, -12, "slti {reg1}, {reg2}, {imm}"), "Slti"); } TEST_F(AssemblerRISCV64Test, Sltiu) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Sltiu, -12, "sltiu {reg1}, {reg2}, {imm}"), - "Sltiu"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Sltiu, -12, "sltiu {reg1}, {reg2}, {imm}"), "Sltiu"); } TEST_F(AssemblerRISCV64Test, Xori) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Xori, 11, "xori {reg1}, {reg2}, {imm}"), "Xori"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Xori, 11, "xori {reg1}, {reg2}, {imm}"), "Xori"); } TEST_F(AssemblerRISCV64Test, Ori) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Ori, -12, "ori {reg1}, {reg2}, {imm}"), "Ori"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Ori, -12, "ori {reg1}, {reg2}, {imm}"), "Ori"); } TEST_F(AssemblerRISCV64Test, Andi) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Andi, -12, "andi {reg1}, {reg2}, {imm}"), - "Andi"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Andi, -12, "andi {reg1}, {reg2}, {imm}"), "Andi"); } TEST_F(AssemblerRISCV64Test, Slli) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Slli, 6, "slli {reg1}, {reg2}, {imm}"), "Slli"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Slli, 6, "slli {reg1}, {reg2}, {imm}"), "Slli"); } TEST_F(AssemblerRISCV64Test, Srli) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Srli, 6, "srli {reg1}, {reg2}, {imm}"), "Srli"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Srli, 6, "srli {reg1}, {reg2}, {imm}"), "Srli"); } TEST_F(AssemblerRISCV64Test, Srai) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Srai, 6, "srai {reg1}, {reg2}, {imm}"), "Srai"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Srai, 6, "srai {reg1}, {reg2}, {imm}"), "Srai"); } TEST_F(AssemblerRISCV64Test, Add) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Add, "add {reg1}, {reg2}, {reg3}"), "Add"); + DriverStr(RepeatRRR(&Riscv64Assembler::Add, "add {reg1}, {reg2}, {reg3}"), "Add"); } TEST_F(AssemblerRISCV64Test, Sub) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Sub, "sub {reg1}, {reg2}, {reg3}"), "Sub"); + DriverStr(RepeatRRR(&Riscv64Assembler::Sub, "sub {reg1}, {reg2}, {reg3}"), "Sub"); } TEST_F(AssemblerRISCV64Test, Slt) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Slt, "slt {reg1}, {reg2}, {reg3}"), "Slt"); + DriverStr(RepeatRRR(&Riscv64Assembler::Slt, "slt {reg1}, {reg2}, {reg3}"), "Slt"); } TEST_F(AssemblerRISCV64Test, Sltu) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Sltu, "sltu {reg1}, {reg2}, {reg3}"), "Sltu"); + DriverStr(RepeatRRR(&Riscv64Assembler::Sltu, "sltu {reg1}, {reg2}, {reg3}"), "Sltu"); } TEST_F(AssemblerRISCV64Test, Xor) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Xor, "xor {reg1}, {reg2}, {reg3}"), "Xor"); + DriverStr(RepeatRRR(&Riscv64Assembler::Xor, "xor {reg1}, {reg2}, {reg3}"), "Xor"); } TEST_F(AssemblerRISCV64Test, Or) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Or, "or {reg1}, {reg2}, {reg3}"), "Or"); + DriverStr(RepeatRRR(&Riscv64Assembler::Or, "or {reg1}, {reg2}, {reg3}"), "Or"); } TEST_F(AssemblerRISCV64Test, And) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::And, "and {reg1}, {reg2}, {reg3}"), "And"); + DriverStr(RepeatRRR(&Riscv64Assembler::And, "and {reg1}, {reg2}, {reg3}"), "And"); } TEST_F(AssemblerRISCV64Test, Sll) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Sll, "sll {reg1}, {reg2}, {reg3}"), "Sll"); + DriverStr(RepeatRRR(&Riscv64Assembler::Sll, "sll {reg1}, {reg2}, {reg3}"), "Sll"); } TEST_F(AssemblerRISCV64Test, Srl) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Srl, "srl {reg1}, {reg2}, {reg3}"), "Srl"); + DriverStr(RepeatRRR(&Riscv64Assembler::Srl, "srl {reg1}, {reg2}, {reg3}"), "Srl"); } TEST_F(AssemblerRISCV64Test, Sra) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Sra, "sra {reg1}, {reg2}, {reg3}"), "Sra"); + DriverStr(RepeatRRR(&Riscv64Assembler::Sra, "sra {reg1}, {reg2}, {reg3}"), "Sra"); } TEST_F(AssemblerRISCV64Test, Addiw) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Addiw, -12, "addiw {reg1}, {reg2}, {imm}"), - "Addiw"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Addiw, -12, "addiw {reg1}, {reg2}, {imm}"), "Addiw"); } TEST_F(AssemblerRISCV64Test, Slliw) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Slliw, 5, "slliw {reg1}, {reg2}, {imm}"), - "Slliw"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Slliw, 5, "slliw {reg1}, {reg2}, {imm}"), "Slliw"); } TEST_F(AssemblerRISCV64Test, Srliw) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Srliw, 5, "srliw {reg1}, {reg2}, {imm}"), - "Srliw"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Srliw, 5, "srliw {reg1}, {reg2}, {imm}"), "Srliw"); } TEST_F(AssemblerRISCV64Test, Sraiw) { - DriverStr(RepeatRRIb(&riscv64::Riscv64Assembler::Sraiw, 5, "sraiw {reg1}, {reg2}, {imm}"), - "Sraiw"); + DriverStr(RepeatRRIb(&Riscv64Assembler::Sraiw, 5, "sraiw {reg1}, {reg2}, {imm}"), "Sraiw"); } TEST_F(AssemblerRISCV64Test, Addw) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Addw, "addw {reg1}, {reg2}, {reg3}"), "Addw"); + DriverStr(RepeatRRR(&Riscv64Assembler::Addw, "addw {reg1}, {reg2}, {reg3}"), "Addw"); } TEST_F(AssemblerRISCV64Test, Subw) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Subw, "subw {reg1}, {reg2}, {reg3}"), "Subw"); + DriverStr(RepeatRRR(&Riscv64Assembler::Subw, "subw {reg1}, {reg2}, {reg3}"), "Subw"); } TEST_F(AssemblerRISCV64Test, Sllw) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Sllw, "sllw {reg1}, {reg2}, {reg3}"), "Sllw"); + DriverStr(RepeatRRR(&Riscv64Assembler::Sllw, "sllw {reg1}, {reg2}, {reg3}"), "Sllw"); } TEST_F(AssemblerRISCV64Test, Srlw) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Srlw, "srlw {reg1}, {reg2}, {reg3}"), "Srlw"); + DriverStr(RepeatRRR(&Riscv64Assembler::Srlw, "srlw {reg1}, {reg2}, {reg3}"), "Srlw"); } TEST_F(AssemblerRISCV64Test, Sraw) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Sraw, "sraw {reg1}, {reg2}, {reg3}"), "Sraw"); + DriverStr(RepeatRRR(&Riscv64Assembler::Sraw, "sraw {reg1}, {reg2}, {reg3}"), "Sraw"); } TEST_F(AssemblerRISCV64Test, Ecall) { @@ -1469,499 +1454,455 @@ TEST_F(AssemblerRISCV64Test, FenceI) { } TEST_F(AssemblerRISCV64Test, Mul) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Mul, "mul {reg1}, {reg2}, {reg3}"), "Mul"); + DriverStr(RepeatRRR(&Riscv64Assembler::Mul, "mul {reg1}, {reg2}, {reg3}"), "Mul"); } TEST_F(AssemblerRISCV64Test, Mulh) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Mulh, "mulh {reg1}, {reg2}, {reg3}"), "Mulh"); + DriverStr(RepeatRRR(&Riscv64Assembler::Mulh, "mulh {reg1}, {reg2}, {reg3}"), "Mulh"); } TEST_F(AssemblerRISCV64Test, Mulhsu) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Mulhsu, "mulhsu {reg1}, {reg2}, {reg3}"), "Mulhsu"); + DriverStr(RepeatRRR(&Riscv64Assembler::Mulhsu, "mulhsu {reg1}, {reg2}, {reg3}"), "Mulhsu"); } TEST_F(AssemblerRISCV64Test, Mulhu) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Mulhu, "mulhu {reg1}, {reg2}, {reg3}"), "Mulhu"); + DriverStr(RepeatRRR(&Riscv64Assembler::Mulhu, "mulhu {reg1}, {reg2}, {reg3}"), "Mulhu"); } TEST_F(AssemblerRISCV64Test, Div) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Div, "div {reg1}, {reg2}, {reg3}"), "Div"); + DriverStr(RepeatRRR(&Riscv64Assembler::Div, "div {reg1}, {reg2}, {reg3}"), "Div"); } TEST_F(AssemblerRISCV64Test, Divu) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Divu, "divu {reg1}, {reg2}, {reg3}"), "Divu"); + DriverStr(RepeatRRR(&Riscv64Assembler::Divu, "divu {reg1}, {reg2}, {reg3}"), "Divu"); } TEST_F(AssemblerRISCV64Test, Rem) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Rem, "rem {reg1}, {reg2}, {reg3}"), "Rem"); + DriverStr(RepeatRRR(&Riscv64Assembler::Rem, "rem {reg1}, {reg2}, {reg3}"), "Rem"); } TEST_F(AssemblerRISCV64Test, Remu) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Remu, "remu {reg1}, {reg2}, {reg3}"), "Remu"); + DriverStr(RepeatRRR(&Riscv64Assembler::Remu, "remu {reg1}, {reg2}, {reg3}"), "Remu"); } TEST_F(AssemblerRISCV64Test, Mulw) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Mulw, "mulw {reg1}, {reg2}, {reg3}"), "Mulw"); + DriverStr(RepeatRRR(&Riscv64Assembler::Mulw, "mulw {reg1}, {reg2}, {reg3}"), "Mulw"); } TEST_F(AssemblerRISCV64Test, Divw) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Divw, "divw {reg1}, {reg2}, {reg3}"), "Divw"); + DriverStr(RepeatRRR(&Riscv64Assembler::Divw, "divw {reg1}, {reg2}, {reg3}"), "Divw"); } TEST_F(AssemblerRISCV64Test, Divuw) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Divuw, "divuw {reg1}, {reg2}, {reg3}"), "Divuw"); + DriverStr(RepeatRRR(&Riscv64Assembler::Divuw, "divuw {reg1}, {reg2}, {reg3}"), "Divuw"); } TEST_F(AssemblerRISCV64Test, Remw) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Remw, "remw {reg1}, {reg2}, {reg3}"), "Remw"); + DriverStr(RepeatRRR(&Riscv64Assembler::Remw, "remw {reg1}, {reg2}, {reg3}"), "Remw"); } TEST_F(AssemblerRISCV64Test, Remuw) { - DriverStr(RepeatRRR(&riscv64::Riscv64Assembler::Remuw, "remuw {reg1}, {reg2}, {reg3}"), "Remuw"); + DriverStr(RepeatRRR(&Riscv64Assembler::Remuw, "remuw {reg1}, {reg2}, {reg3}"), "Remuw"); } TEST_F(AssemblerRISCV64Test, LrW) { - DriverStr(RepeatRRAqRl(&riscv64::Riscv64Assembler::LrW, "lr.w{aqrl} {reg1}, ({reg2})"), "LrW"); + DriverStr(RepeatRRAqRl(&Riscv64Assembler::LrW, "lr.w{aqrl} {reg1}, ({reg2})"), "LrW"); } TEST_F(AssemblerRISCV64Test, LrD) { - DriverStr(RepeatRRAqRl(&riscv64::Riscv64Assembler::LrD, "lr.d{aqrl} {reg1}, ({reg2})"), "LrD"); + DriverStr(RepeatRRAqRl(&Riscv64Assembler::LrD, "lr.d{aqrl} {reg1}, ({reg2})"), "LrD"); } TEST_F(AssemblerRISCV64Test, ScW) { - DriverStr(RepeatRRRAqRl(&riscv64::Riscv64Assembler::ScW, "sc.w{aqrl} {reg1}, {reg2}, ({reg3})"), - "ScW"); + DriverStr(RepeatRRRAqRl(&Riscv64Assembler::ScW, "sc.w{aqrl} {reg1}, {reg2}, ({reg3})"), "ScW"); } TEST_F(AssemblerRISCV64Test, ScD) { - DriverStr(RepeatRRRAqRl(&riscv64::Riscv64Assembler::ScD, "sc.d{aqrl} {reg1}, {reg2}, ({reg3})"), - "ScD"); + DriverStr(RepeatRRRAqRl(&Riscv64Assembler::ScD, "sc.d{aqrl} {reg1}, {reg2}, ({reg3})"), "ScD"); } TEST_F(AssemblerRISCV64Test, AmoSwapW) { - DriverStr(RepeatRRRAqRl( - &riscv64::Riscv64Assembler::AmoSwapW, "amoswap.w{aqrl} {reg1}, {reg2}, ({reg3})"), + DriverStr(RepeatRRRAqRl(&Riscv64Assembler::AmoSwapW, "amoswap.w{aqrl} {reg1}, {reg2}, ({reg3})"), "AmoSwapW"); } TEST_F(AssemblerRISCV64Test, AmoSwapD) { - DriverStr(RepeatRRRAqRl( - &riscv64::Riscv64Assembler::AmoSwapD, "amoswap.d{aqrl} {reg1}, {reg2}, ({reg3})"), + DriverStr(RepeatRRRAqRl(&Riscv64Assembler::AmoSwapD, "amoswap.d{aqrl} {reg1}, {reg2}, ({reg3})"), "AmoSwapD"); } TEST_F(AssemblerRISCV64Test, AmoAddW) { - DriverStr(RepeatRRRAqRl( - &riscv64::Riscv64Assembler::AmoAddW, "amoadd.w{aqrl} {reg1}, {reg2}, ({reg3})"), + DriverStr(RepeatRRRAqRl(&Riscv64Assembler::AmoAddW, "amoadd.w{aqrl} {reg1}, {reg2}, ({reg3})"), "AmoAddW"); } TEST_F(AssemblerRISCV64Test, AmoAddD) { - DriverStr(RepeatRRRAqRl( - &riscv64::Riscv64Assembler::AmoAddD, "amoadd.d{aqrl} {reg1}, {reg2}, ({reg3})"), + DriverStr(RepeatRRRAqRl(&Riscv64Assembler::AmoAddD, "amoadd.d{aqrl} {reg1}, {reg2}, ({reg3})"), "AmoAddD"); } TEST_F(AssemblerRISCV64Test, AmoXorW) { - DriverStr(RepeatRRRAqRl( - &riscv64::Riscv64Assembler::AmoXorW, "amoxor.w{aqrl} {reg1}, {reg2}, ({reg3})"), + DriverStr(RepeatRRRAqRl(&Riscv64Assembler::AmoXorW, "amoxor.w{aqrl} {reg1}, {reg2}, ({reg3})"), "AmoXorW"); } TEST_F(AssemblerRISCV64Test, AmoXorD) { - DriverStr(RepeatRRRAqRl( - &riscv64::Riscv64Assembler::AmoXorD, "amoxor.d{aqrl} {reg1}, {reg2}, ({reg3})"), + DriverStr(RepeatRRRAqRl(&Riscv64Assembler::AmoXorD, "amoxor.d{aqrl} {reg1}, {reg2}, ({reg3})"), "AmoXorD"); } TEST_F(AssemblerRISCV64Test, AmoAndW) { - DriverStr(RepeatRRRAqRl( - &riscv64::Riscv64Assembler::AmoAndW, "amoand.w{aqrl} {reg1}, {reg2}, ({reg3})"), + DriverStr(RepeatRRRAqRl(&Riscv64Assembler::AmoAndW, "amoand.w{aqrl} {reg1}, {reg2}, ({reg3})"), "AmoAndW"); } TEST_F(AssemblerRISCV64Test, AmoAndD) { - DriverStr(RepeatRRRAqRl( - &riscv64::Riscv64Assembler::AmoAndD, "amoand.d{aqrl} {reg1}, {reg2}, ({reg3})"), + DriverStr(RepeatRRRAqRl(&Riscv64Assembler::AmoAndD, "amoand.d{aqrl} {reg1}, {reg2}, ({reg3})"), "AmoAndD"); } TEST_F(AssemblerRISCV64Test, AmoOrW) { - DriverStr(RepeatRRRAqRl( - &riscv64::Riscv64Assembler::AmoOrW, "amoor.w{aqrl} {reg1}, {reg2}, ({reg3})"), + DriverStr(RepeatRRRAqRl(&Riscv64Assembler::AmoOrW, "amoor.w{aqrl} {reg1}, {reg2}, ({reg3})"), "AmoOrW"); } TEST_F(AssemblerRISCV64Test, AmoOrD) { - DriverStr(RepeatRRRAqRl( - &riscv64::Riscv64Assembler::AmoOrD, "amoor.d{aqrl} {reg1}, {reg2}, ({reg3})"), + DriverStr(RepeatRRRAqRl(&Riscv64Assembler::AmoOrD, "amoor.d{aqrl} {reg1}, {reg2}, ({reg3})"), "AmoOrD"); } TEST_F(AssemblerRISCV64Test, AmoMinW) { - DriverStr(RepeatRRRAqRl( - &riscv64::Riscv64Assembler::AmoMinW, "amomin.w{aqrl} {reg1}, {reg2}, ({reg3})"), + DriverStr(RepeatRRRAqRl(&Riscv64Assembler::AmoMinW, "amomin.w{aqrl} {reg1}, {reg2}, ({reg3})"), "AmoMinW"); } TEST_F(AssemblerRISCV64Test, AmoMinD) { - DriverStr(RepeatRRRAqRl( - &riscv64::Riscv64Assembler::AmoMinD, "amomin.d{aqrl} {reg1}, {reg2}, ({reg3})"), + DriverStr(RepeatRRRAqRl(&Riscv64Assembler::AmoMinD, "amomin.d{aqrl} {reg1}, {reg2}, ({reg3})"), "AmoMinD"); } TEST_F(AssemblerRISCV64Test, AmoMaxW) { - DriverStr(RepeatRRRAqRl( - &riscv64::Riscv64Assembler::AmoMaxW, "amomax.w{aqrl} {reg1}, {reg2}, ({reg3})"), + DriverStr(RepeatRRRAqRl(&Riscv64Assembler::AmoMaxW, "amomax.w{aqrl} {reg1}, {reg2}, ({reg3})"), "AmoMaxW"); } TEST_F(AssemblerRISCV64Test, AmoMaxD) { - DriverStr(RepeatRRRAqRl( - &riscv64::Riscv64Assembler::AmoMaxD, "amomax.d{aqrl} {reg1}, {reg2}, ({reg3})"), + DriverStr(RepeatRRRAqRl(&Riscv64Assembler::AmoMaxD, "amomax.d{aqrl} {reg1}, {reg2}, ({reg3})"), "AmoMaxD"); } TEST_F(AssemblerRISCV64Test, AmoMinuW) { - DriverStr(RepeatRRRAqRl( - &riscv64::Riscv64Assembler::AmoMinuW, "amominu.w{aqrl} {reg1}, {reg2}, ({reg3})"), + DriverStr(RepeatRRRAqRl(&Riscv64Assembler::AmoMinuW, "amominu.w{aqrl} {reg1}, {reg2}, ({reg3})"), "AmoMinuW"); } TEST_F(AssemblerRISCV64Test, AmoMinuD) { - DriverStr(RepeatRRRAqRl( - &riscv64::Riscv64Assembler::AmoMinuD, "amominu.d{aqrl} {reg1}, {reg2}, ({reg3})"), + DriverStr(RepeatRRRAqRl(&Riscv64Assembler::AmoMinuD, "amominu.d{aqrl} {reg1}, {reg2}, ({reg3})"), "AmoMinuD"); } TEST_F(AssemblerRISCV64Test, AmoMaxuW) { - DriverStr(RepeatRRRAqRl( - &riscv64::Riscv64Assembler::AmoMaxuW, "amomaxu.w{aqrl} {reg1}, {reg2}, ({reg3})"), + DriverStr(RepeatRRRAqRl(&Riscv64Assembler::AmoMaxuW, "amomaxu.w{aqrl} {reg1}, {reg2}, ({reg3})"), "AmoMaxuW"); } TEST_F(AssemblerRISCV64Test, AmoMaxuD) { - DriverStr(RepeatRRRAqRl( - &riscv64::Riscv64Assembler::AmoMaxuD, "amomaxu.d{aqrl} {reg1}, {reg2}, ({reg3})"), + DriverStr(RepeatRRRAqRl(&Riscv64Assembler::AmoMaxuD, "amomaxu.d{aqrl} {reg1}, {reg2}, ({reg3})"), "AmoMaxuD"); } TEST_F(AssemblerRISCV64Test, Csrrw) { - DriverStr(RepeatCsrrX(&riscv64::Riscv64Assembler::Csrrw, "csrrw {reg1}, {csr}, {reg2}"), - "Csrrw"); + DriverStr(RepeatCsrrX(&Riscv64Assembler::Csrrw, "csrrw {reg1}, {csr}, {reg2}"), "Csrrw"); } TEST_F(AssemblerRISCV64Test, Csrrs) { - DriverStr(RepeatCsrrX(&riscv64::Riscv64Assembler::Csrrs, "csrrs {reg1}, {csr}, {reg2}"), - "Csrrs"); + DriverStr(RepeatCsrrX(&Riscv64Assembler::Csrrs, "csrrs {reg1}, {csr}, {reg2}"), "Csrrs"); } TEST_F(AssemblerRISCV64Test, Csrrc) { - DriverStr(RepeatCsrrX(&riscv64::Riscv64Assembler::Csrrc, "csrrc {reg1}, {csr}, {reg2}"), - "Csrrc"); + DriverStr(RepeatCsrrX(&Riscv64Assembler::Csrrc, "csrrc {reg1}, {csr}, {reg2}"), "Csrrc"); } TEST_F(AssemblerRISCV64Test, Csrrwi) { - DriverStr(RepeatCsrrXi(&riscv64::Riscv64Assembler::Csrrwi, "csrrwi {reg}, {csr}, {uimm}"), - "Csrrwi"); + DriverStr(RepeatCsrrXi(&Riscv64Assembler::Csrrwi, "csrrwi {reg}, {csr}, {uimm}"), "Csrrwi"); } TEST_F(AssemblerRISCV64Test, Csrrsi) { - DriverStr(RepeatCsrrXi(&riscv64::Riscv64Assembler::Csrrsi, "csrrsi {reg}, {csr}, {uimm}"), - "Csrrsi"); + DriverStr(RepeatCsrrXi(&Riscv64Assembler::Csrrsi, "csrrsi {reg}, {csr}, {uimm}"), "Csrrsi"); } TEST_F(AssemblerRISCV64Test, Csrrci) { - DriverStr(RepeatCsrrXi(&riscv64::Riscv64Assembler::Csrrci, "csrrci {reg}, {csr}, {uimm}"), - "Csrrci"); + DriverStr(RepeatCsrrXi(&Riscv64Assembler::Csrrci, "csrrci {reg}, {csr}, {uimm}"), "Csrrci"); } TEST_F(AssemblerRISCV64Test, FLw) { - DriverStr(RepeatFRIb(&riscv64::Riscv64Assembler::FLw, -12, "flw {reg1}, {imm}({reg2})"), "FLw"); + DriverStr(RepeatFRIb(&Riscv64Assembler::FLw, -12, "flw {reg1}, {imm}({reg2})"), "FLw"); } TEST_F(AssemblerRISCV64Test, FLd) { - DriverStr(RepeatFRIb(&riscv64::Riscv64Assembler::FLd, -12, "fld {reg1}, {imm}({reg2})"), "FLw"); + DriverStr(RepeatFRIb(&Riscv64Assembler::FLd, -12, "fld {reg1}, {imm}({reg2})"), "FLw"); } TEST_F(AssemblerRISCV64Test, FSw) { - DriverStr(RepeatFRIb(&riscv64::Riscv64Assembler::FSw, 2, "fsw {reg1}, {imm}({reg2})"), "FSw"); + DriverStr(RepeatFRIb(&Riscv64Assembler::FSw, 2, "fsw {reg1}, {imm}({reg2})"), "FSw"); } TEST_F(AssemblerRISCV64Test, FSd) { - DriverStr(RepeatFRIb(&riscv64::Riscv64Assembler::FSd, 2, "fsd {reg1}, {imm}({reg2})"), "FSd"); + DriverStr(RepeatFRIb(&Riscv64Assembler::FSd, 2, "fsd {reg1}, {imm}({reg2})"), "FSd"); } TEST_F(AssemblerRISCV64Test, FMAddS) { - DriverStr(RepeatFFFFRoundingMode(&riscv64::Riscv64Assembler::FMAddS, + DriverStr(RepeatFFFFRoundingMode(&Riscv64Assembler::FMAddS, "fmadd.s {reg1}, {reg2}, {reg3}, {reg4}, {rm}"), "FMAddS"); } TEST_F(AssemblerRISCV64Test, FMAddS_Default) { - DriverStr(RepeatFFFF(&riscv64::Riscv64Assembler::FMAddS, - "fmadd.s {reg1}, {reg2}, {reg3}, {reg4}"), "FMAddS_Default"); + DriverStr(RepeatFFFF(&Riscv64Assembler::FMAddS, "fmadd.s {reg1}, {reg2}, {reg3}, {reg4}"), + "FMAddS_Default"); } TEST_F(AssemblerRISCV64Test, FMAddD) { - DriverStr(RepeatFFFFRoundingMode(&riscv64::Riscv64Assembler::FMAddD, + DriverStr(RepeatFFFFRoundingMode(&Riscv64Assembler::FMAddD, "fmadd.d {reg1}, {reg2}, {reg3}, {reg4}, {rm}"), "FMAddD"); } TEST_F(AssemblerRISCV64Test, FMAddD_Default) { - DriverStr(RepeatFFFF(&riscv64::Riscv64Assembler::FMAddD, - "fmadd.d {reg1}, {reg2}, {reg3}, {reg4}"), "FMAddD_Default"); + DriverStr(RepeatFFFF(&Riscv64Assembler::FMAddD, "fmadd.d {reg1}, {reg2}, {reg3}, {reg4}"), + "FMAddD_Default"); } TEST_F(AssemblerRISCV64Test, FMSubS) { - DriverStr(RepeatFFFFRoundingMode(&riscv64::Riscv64Assembler::FMSubS, + DriverStr(RepeatFFFFRoundingMode(&Riscv64Assembler::FMSubS, "fmsub.s {reg1}, {reg2}, {reg3}, {reg4}, {rm}"), "FMSubS"); } TEST_F(AssemblerRISCV64Test, FMSubS_Default) { - DriverStr(RepeatFFFF(&riscv64::Riscv64Assembler::FMSubS, - "fmsub.s {reg1}, {reg2}, {reg3}, {reg4}"), "FMSubS_Default"); + DriverStr(RepeatFFFF(&Riscv64Assembler::FMSubS, "fmsub.s {reg1}, {reg2}, {reg3}, {reg4}"), + "FMSubS_Default"); } TEST_F(AssemblerRISCV64Test, FMSubD) { - DriverStr(RepeatFFFFRoundingMode(&riscv64::Riscv64Assembler::FMSubD, + DriverStr(RepeatFFFFRoundingMode(&Riscv64Assembler::FMSubD, "fmsub.d {reg1}, {reg2}, {reg3}, {reg4}, {rm}"), "FMSubD"); } TEST_F(AssemblerRISCV64Test, FMSubD_Default) { - DriverStr(RepeatFFFF(&riscv64::Riscv64Assembler::FMSubD, - "fmsub.d {reg1}, {reg2}, {reg3}, {reg4}"), "FMSubD_Default"); + DriverStr(RepeatFFFF(&Riscv64Assembler::FMSubD, "fmsub.d {reg1}, {reg2}, {reg3}, {reg4}"), + "FMSubD_Default"); } TEST_F(AssemblerRISCV64Test, FNMSubS) { - DriverStr(RepeatFFFFRoundingMode(&riscv64::Riscv64Assembler::FNMSubS, + DriverStr(RepeatFFFFRoundingMode(&Riscv64Assembler::FNMSubS, "fnmsub.s {reg1}, {reg2}, {reg3}, {reg4}, {rm}"), "FNMSubS"); } TEST_F(AssemblerRISCV64Test, FNMSubS_Default) { - DriverStr(RepeatFFFF(&riscv64::Riscv64Assembler::FNMSubS, - "fnmsub.s {reg1}, {reg2}, {reg3}, {reg4}"), "FNMSubS_Default"); + DriverStr(RepeatFFFF(&Riscv64Assembler::FNMSubS, "fnmsub.s {reg1}, {reg2}, {reg3}, {reg4}"), + "FNMSubS_Default"); } TEST_F(AssemblerRISCV64Test, FNMSubD) { - DriverStr(RepeatFFFFRoundingMode(&riscv64::Riscv64Assembler::FNMSubD, + DriverStr(RepeatFFFFRoundingMode(&Riscv64Assembler::FNMSubD, "fnmsub.d {reg1}, {reg2}, {reg3}, {reg4}, {rm}"), "FNMSubD"); } TEST_F(AssemblerRISCV64Test, FNMSubD_Default) { - DriverStr(RepeatFFFF(&riscv64::Riscv64Assembler::FNMSubD, - "fnmsub.d {reg1}, {reg2}, {reg3}, {reg4}"), "FNMSubD_Default"); + DriverStr(RepeatFFFF(&Riscv64Assembler::FNMSubD, "fnmsub.d {reg1}, {reg2}, {reg3}, {reg4}"), + "FNMSubD_Default"); } TEST_F(AssemblerRISCV64Test, FNMAddS) { - DriverStr(RepeatFFFFRoundingMode(&riscv64::Riscv64Assembler::FNMAddS, + DriverStr(RepeatFFFFRoundingMode(&Riscv64Assembler::FNMAddS, "fnmadd.s {reg1}, {reg2}, {reg3}, {reg4}, {rm}"), "FNMAddS"); } TEST_F(AssemblerRISCV64Test, FNMAddS_Default) { - DriverStr(RepeatFFFF(&riscv64::Riscv64Assembler::FNMAddS, - "fnmadd.s {reg1}, {reg2}, {reg3}, {reg4}"), "FNMAddS_Default"); + DriverStr(RepeatFFFF(&Riscv64Assembler::FNMAddS, "fnmadd.s {reg1}, {reg2}, {reg3}, {reg4}"), + "FNMAddS_Default"); } TEST_F(AssemblerRISCV64Test, FNMAddD) { - DriverStr(RepeatFFFFRoundingMode(&riscv64::Riscv64Assembler::FNMAddD, + DriverStr(RepeatFFFFRoundingMode(&Riscv64Assembler::FNMAddD, "fnmadd.d {reg1}, {reg2}, {reg3}, {reg4}, {rm}"), "FNMAddD"); } TEST_F(AssemblerRISCV64Test, FNMAddD_Default) { - DriverStr(RepeatFFFF(&riscv64::Riscv64Assembler::FNMAddD, - "fnmadd.d {reg1}, {reg2}, {reg3}, {reg4}"), "FNMAddD_Default"); + DriverStr(RepeatFFFF(&Riscv64Assembler::FNMAddD, "fnmadd.d {reg1}, {reg2}, {reg3}, {reg4}"), + "FNMAddD_Default"); } TEST_F(AssemblerRISCV64Test, FAddS) { - DriverStr(RepeatFFFRoundingMode(&riscv64::Riscv64Assembler::FAddS, - "fadd.s {reg1}, {reg2}, {reg3}, {rm}"), "FAddS"); + DriverStr(RepeatFFFRoundingMode(&Riscv64Assembler::FAddS, "fadd.s {reg1}, {reg2}, {reg3}, {rm}"), + "FAddS"); } TEST_F(AssemblerRISCV64Test, FAddS_Default) { - DriverStr(RepeatFFF(&riscv64::Riscv64Assembler::FAddS, - "fadd.s {reg1}, {reg2}, {reg3}"), "FAddS_Default"); + DriverStr(RepeatFFF(&Riscv64Assembler::FAddS, "fadd.s {reg1}, {reg2}, {reg3}"), "FAddS_Default"); } TEST_F(AssemblerRISCV64Test, FAddD) { - DriverStr(RepeatFFFRoundingMode(&riscv64::Riscv64Assembler::FAddD, - "fadd.d {reg1}, {reg2}, {reg3}, {rm}"), "FAddD"); + DriverStr(RepeatFFFRoundingMode(&Riscv64Assembler::FAddD, "fadd.d {reg1}, {reg2}, {reg3}, {rm}"), + "FAddD"); } TEST_F(AssemblerRISCV64Test, FAddD_Default) { - DriverStr(RepeatFFF(&riscv64::Riscv64Assembler::FAddD, - "fadd.d {reg1}, {reg2}, {reg3}"), "FAddD_Default"); + DriverStr(RepeatFFF(&Riscv64Assembler::FAddD, "fadd.d {reg1}, {reg2}, {reg3}"), "FAddD_Default"); } TEST_F(AssemblerRISCV64Test, FSubS) { - DriverStr(RepeatFFFRoundingMode(&riscv64::Riscv64Assembler::FSubS, - "fsub.s {reg1}, {reg2}, {reg3}, {rm}"), "FSubS"); + DriverStr(RepeatFFFRoundingMode(&Riscv64Assembler::FSubS, "fsub.s {reg1}, {reg2}, {reg3}, {rm}"), + "FSubS"); } TEST_F(AssemblerRISCV64Test, FSubS_Default) { - DriverStr(RepeatFFF(&riscv64::Riscv64Assembler::FSubS, - "fsub.s {reg1}, {reg2}, {reg3}"), "FSubS_Default"); + DriverStr(RepeatFFF(&Riscv64Assembler::FSubS, "fsub.s {reg1}, {reg2}, {reg3}"), "FSubS_Default"); } TEST_F(AssemblerRISCV64Test, FSubD) { - DriverStr(RepeatFFFRoundingMode(&riscv64::Riscv64Assembler::FSubD, - "fsub.d {reg1}, {reg2}, {reg3}, {rm}"), "FSubD"); + DriverStr(RepeatFFFRoundingMode(&Riscv64Assembler::FSubD, "fsub.d {reg1}, {reg2}, {reg3}, {rm}"), + "FSubD"); } TEST_F(AssemblerRISCV64Test, FSubD_Default) { - DriverStr(RepeatFFF(&riscv64::Riscv64Assembler::FSubD, - "fsub.d {reg1}, {reg2}, {reg3}"), "FSubD_Default"); + DriverStr(RepeatFFF(&Riscv64Assembler::FSubD, "fsub.d {reg1}, {reg2}, {reg3}"), "FSubD_Default"); } TEST_F(AssemblerRISCV64Test, FMulS) { - DriverStr(RepeatFFFRoundingMode(&riscv64::Riscv64Assembler::FMulS, - "fmul.s {reg1}, {reg2}, {reg3}, {rm}"), "FMulS"); + DriverStr(RepeatFFFRoundingMode(&Riscv64Assembler::FMulS, "fmul.s {reg1}, {reg2}, {reg3}, {rm}"), + "FMulS"); } TEST_F(AssemblerRISCV64Test, FMulS_Default) { - DriverStr(RepeatFFF(&riscv64::Riscv64Assembler::FMulS, - "fmul.s {reg1}, {reg2}, {reg3}"), "FMulS_Default"); + DriverStr(RepeatFFF(&Riscv64Assembler::FMulS, "fmul.s {reg1}, {reg2}, {reg3}"), "FMulS_Default"); } TEST_F(AssemblerRISCV64Test, FMulD) { - DriverStr(RepeatFFFRoundingMode(&riscv64::Riscv64Assembler::FMulD, - "fmul.d {reg1}, {reg2}, {reg3}, {rm}"), "FMulD"); + DriverStr(RepeatFFFRoundingMode(&Riscv64Assembler::FMulD, "fmul.d {reg1}, {reg2}, {reg3}, {rm}"), + "FMulD"); } TEST_F(AssemblerRISCV64Test, FMulD_Default) { - DriverStr(RepeatFFF(&riscv64::Riscv64Assembler::FMulD, - "fmul.d {reg1}, {reg2}, {reg3}"), "FMulD_Default"); + DriverStr(RepeatFFF(&Riscv64Assembler::FMulD, "fmul.d {reg1}, {reg2}, {reg3}"), "FMulD_Default"); } TEST_F(AssemblerRISCV64Test, FDivS) { - DriverStr(RepeatFFFRoundingMode(&riscv64::Riscv64Assembler::FDivS, - "fdiv.s {reg1}, {reg2}, {reg3}, {rm}"), "FDivS"); + DriverStr(RepeatFFFRoundingMode(&Riscv64Assembler::FDivS, "fdiv.s {reg1}, {reg2}, {reg3}, {rm}"), + "FDivS"); } TEST_F(AssemblerRISCV64Test, FDivS_Default) { - DriverStr(RepeatFFF(&riscv64::Riscv64Assembler::FDivS, - "fdiv.s {reg1}, {reg2}, {reg3}"), "FDivS_Default"); + DriverStr(RepeatFFF(&Riscv64Assembler::FDivS, "fdiv.s {reg1}, {reg2}, {reg3}"), "FDivS_Default"); } TEST_F(AssemblerRISCV64Test, FDivD) { - DriverStr(RepeatFFFRoundingMode(&riscv64::Riscv64Assembler::FDivD, - "fdiv.d {reg1}, {reg2}, {reg3}, {rm}"), "FDivD"); + DriverStr(RepeatFFFRoundingMode(&Riscv64Assembler::FDivD, "fdiv.d {reg1}, {reg2}, {reg3}, {rm}"), + "FDivD"); } TEST_F(AssemblerRISCV64Test, FDivD_Default) { - DriverStr(RepeatFFF(&riscv64::Riscv64Assembler::FDivD, - "fdiv.d {reg1}, {reg2}, {reg3}"), "FDivD_Default"); + DriverStr(RepeatFFF(&Riscv64Assembler::FDivD, "fdiv.d {reg1}, {reg2}, {reg3}"), "FDivD_Default"); } TEST_F(AssemblerRISCV64Test, FSqrtS) { - DriverStr(RepeatFFRoundingMode(&riscv64::Riscv64Assembler::FSqrtS, - "fsqrt.s {reg1}, {reg2}, {rm}"), "FSqrtS"); + DriverStr(RepeatFFRoundingMode(&Riscv64Assembler::FSqrtS, "fsqrt.s {reg1}, {reg2}, {rm}"), + "FSqrtS"); } TEST_F(AssemblerRISCV64Test, FSqrtS_Default) { - DriverStr(RepeatFF(&riscv64::Riscv64Assembler::FSqrtS, - "fsqrt.s {reg1}, {reg2}"), "FSqrtS_Default"); + DriverStr(RepeatFF(&Riscv64Assembler::FSqrtS, "fsqrt.s {reg1}, {reg2}"), "FSqrtS_Default"); } TEST_F(AssemblerRISCV64Test, FSqrtD) { - DriverStr(RepeatFFRoundingMode(&riscv64::Riscv64Assembler::FSqrtD, - "fsqrt.d {reg1}, {reg2}, {rm}"), "FSqrtD"); + DriverStr(RepeatFFRoundingMode(&Riscv64Assembler::FSqrtD, "fsqrt.d {reg1}, {reg2}, {rm}"), + "FSqrtD"); } TEST_F(AssemblerRISCV64Test, FSqrtD_Default) { - DriverStr(RepeatFF(&riscv64::Riscv64Assembler::FSqrtD, - "fsqrt.d {reg1}, {reg2}"), "FSqrtD_Default"); + DriverStr(RepeatFF(&Riscv64Assembler::FSqrtD, "fsqrt.d {reg1}, {reg2}"), "FSqrtD_Default"); } TEST_F(AssemblerRISCV64Test, FSgnjS) { - DriverStr(RepeatFFF(&riscv64::Riscv64Assembler::FSgnjS, "fsgnj.s {reg1}, {reg2}, {reg3}"), - "FSgnjS"); + DriverStr(RepeatFFF(&Riscv64Assembler::FSgnjS, "fsgnj.s {reg1}, {reg2}, {reg3}"), "FSgnjS"); } TEST_F(AssemblerRISCV64Test, FSgnjD) { - DriverStr(RepeatFFF(&riscv64::Riscv64Assembler::FSgnjD, "fsgnj.d {reg1}, {reg2}, {reg3}"), - "FSgnjD"); + DriverStr(RepeatFFF(&Riscv64Assembler::FSgnjD, "fsgnj.d {reg1}, {reg2}, {reg3}"), "FSgnjD"); } TEST_F(AssemblerRISCV64Test, FSgnjnS) { - DriverStr(RepeatFFF(&riscv64::Riscv64Assembler::FSgnjnS, "fsgnjn.s {reg1}, {reg2}, {reg3}"), - "FSgnjnS"); + DriverStr(RepeatFFF(&Riscv64Assembler::FSgnjnS, "fsgnjn.s {reg1}, {reg2}, {reg3}"), "FSgnjnS"); } TEST_F(AssemblerRISCV64Test, FSgnjnD) { - DriverStr(RepeatFFF(&riscv64::Riscv64Assembler::FSgnjnD, "fsgnjn.d {reg1}, {reg2}, {reg3}"), - "FSgnjnD"); + DriverStr(RepeatFFF(&Riscv64Assembler::FSgnjnD, "fsgnjn.d {reg1}, {reg2}, {reg3}"), "FSgnjnD"); } TEST_F(AssemblerRISCV64Test, FSgnjxS) { - DriverStr(RepeatFFF(&riscv64::Riscv64Assembler::FSgnjxS, "fsgnjx.s {reg1}, {reg2}, {reg3}"), - "FSgnjxS"); + DriverStr(RepeatFFF(&Riscv64Assembler::FSgnjxS, "fsgnjx.s {reg1}, {reg2}, {reg3}"), "FSgnjxS"); } TEST_F(AssemblerRISCV64Test, FSgnjxD) { - DriverStr(RepeatFFF(&riscv64::Riscv64Assembler::FSgnjxD, "fsgnjx.d {reg1}, {reg2}, {reg3}"), - "FSgnjxD"); + DriverStr(RepeatFFF(&Riscv64Assembler::FSgnjxD, "fsgnjx.d {reg1}, {reg2}, {reg3}"), "FSgnjxD"); } TEST_F(AssemblerRISCV64Test, FMinS) { - DriverStr(RepeatFFF(&riscv64::Riscv64Assembler::FMinS, "fmin.s {reg1}, {reg2}, {reg3}"), "FMinS"); + DriverStr(RepeatFFF(&Riscv64Assembler::FMinS, "fmin.s {reg1}, {reg2}, {reg3}"), "FMinS"); } TEST_F(AssemblerRISCV64Test, FMinD) { - DriverStr(RepeatFFF(&riscv64::Riscv64Assembler::FMinD, "fmin.d {reg1}, {reg2}, {reg3}"), "FMinD"); + DriverStr(RepeatFFF(&Riscv64Assembler::FMinD, "fmin.d {reg1}, {reg2}, {reg3}"), "FMinD"); } TEST_F(AssemblerRISCV64Test, FMaxS) { - DriverStr(RepeatFFF(&riscv64::Riscv64Assembler::FMaxS, "fmax.s {reg1}, {reg2}, {reg3}"), "FMaxS"); + DriverStr(RepeatFFF(&Riscv64Assembler::FMaxS, "fmax.s {reg1}, {reg2}, {reg3}"), "FMaxS"); } TEST_F(AssemblerRISCV64Test, FMaxD) { - DriverStr(RepeatFFF(&riscv64::Riscv64Assembler::FMaxD, "fmax.d {reg1}, {reg2}, {reg3}"), "FMaxD"); + DriverStr(RepeatFFF(&Riscv64Assembler::FMaxD, "fmax.d {reg1}, {reg2}, {reg3}"), "FMaxD"); } TEST_F(AssemblerRISCV64Test, FCvtSD) { - DriverStr(RepeatFFRoundingMode(&riscv64::Riscv64Assembler::FCvtSD, - "fcvt.s.d {reg1}, {reg2}, {rm}"), "FCvtSD"); + DriverStr(RepeatFFRoundingMode(&Riscv64Assembler::FCvtSD, "fcvt.s.d {reg1}, {reg2}, {rm}"), + "FCvtSD"); } TEST_F(AssemblerRISCV64Test, FCvtSD_Default) { - DriverStr(RepeatFF(&riscv64::Riscv64Assembler::FCvtSD, - "fcvt.s.d {reg1}, {reg2}"), "FCvtSD_Default"); + DriverStr(RepeatFF(&Riscv64Assembler::FCvtSD, "fcvt.s.d {reg1}, {reg2}"), "FCvtSD_Default"); } // This conversion is lossless, so the rounding mode is meaningless and the assembler we're // testing against does not even accept the rounding mode argument, so this test is disabled. TEST_F(AssemblerRISCV64Test, DISABLED_FCvtDS) { - DriverStr(RepeatFFRoundingMode(&riscv64::Riscv64Assembler::FCvtDS, - "fcvt.d.s {reg1}, {reg2}, {rm}"), "FCvtDS"); + DriverStr(RepeatFFRoundingMode(&Riscv64Assembler::FCvtDS, "fcvt.d.s {reg1}, {reg2}, {rm}"), + "FCvtDS"); } TEST_F(AssemblerRISCV64Test, FCvtDS_Default) { - DriverStr(RepeatFF(&riscv64::Riscv64Assembler::FCvtDS, - "fcvt.d.s {reg1}, {reg2}"), "FCvtDS_Default"); + DriverStr(RepeatFF(&Riscv64Assembler::FCvtDS, "fcvt.d.s {reg1}, {reg2}"), "FCvtDS_Default"); } TEST_F(AssemblerRISCV64Test, FEqS) { - DriverStr(RepeatRFF(&riscv64::Riscv64Assembler::FEqS, "feq.s {reg1}, {reg2}, {reg3}"), "FEqS"); + DriverStr(RepeatRFF(&Riscv64Assembler::FEqS, "feq.s {reg1}, {reg2}, {reg3}"), "FEqS"); } TEST_F(AssemblerRISCV64Test, FEqD) { - DriverStr(RepeatRFF(&riscv64::Riscv64Assembler::FEqD, "feq.d {reg1}, {reg2}, {reg3}"), "FEqD"); + DriverStr(RepeatRFF(&Riscv64Assembler::FEqD, "feq.d {reg1}, {reg2}, {reg3}"), "FEqD"); } TEST_F(AssemblerRISCV64Test, FLtS) { - DriverStr(RepeatRFF(&riscv64::Riscv64Assembler::FLtS, "flt.s {reg1}, {reg2}, {reg3}"), "FLtS"); + DriverStr(RepeatRFF(&Riscv64Assembler::FLtS, "flt.s {reg1}, {reg2}, {reg3}"), "FLtS"); } TEST_F(AssemblerRISCV64Test, FLtD) { - DriverStr(RepeatRFF(&riscv64::Riscv64Assembler::FLtD, "flt.d {reg1}, {reg2}, {reg3}"), "FLtD"); + DriverStr(RepeatRFF(&Riscv64Assembler::FLtD, "flt.d {reg1}, {reg2}, {reg3}"), "FLtD"); } TEST_F(AssemblerRISCV64Test, FLeS) { - DriverStr(RepeatRFF(&riscv64::Riscv64Assembler::FLeS, "fle.s {reg1}, {reg2}, {reg3}"), "FLeS"); + DriverStr(RepeatRFF(&Riscv64Assembler::FLeS, "fle.s {reg1}, {reg2}, {reg3}"), "FLeS"); } TEST_F(AssemblerRISCV64Test, FLeD) { - DriverStr(RepeatRFF(&riscv64::Riscv64Assembler::FLeD, "fle.d {reg1}, {reg2}, {reg3}"), "FLeD"); + DriverStr(RepeatRFF(&Riscv64Assembler::FLeD, "fle.d {reg1}, {reg2}, {reg3}"), "FLeD"); } TEST_F(AssemblerRISCV64Test, FCvtWS) { @@ -2113,27 +2054,27 @@ TEST_F(AssemblerRISCV64Test, FCvtDLu_Default) { } TEST_F(AssemblerRISCV64Test, FMvXW) { - DriverStr(RepeatRF(&riscv64::Riscv64Assembler::FMvXW, "fmv.x.w {reg1}, {reg2}"), "FMvXW"); + DriverStr(RepeatRF(&Riscv64Assembler::FMvXW, "fmv.x.w {reg1}, {reg2}"), "FMvXW"); } TEST_F(AssemblerRISCV64Test, FMvXD) { - DriverStr(RepeatRF(&riscv64::Riscv64Assembler::FMvXD, "fmv.x.d {reg1}, {reg2}"), "FMvXD"); + DriverStr(RepeatRF(&Riscv64Assembler::FMvXD, "fmv.x.d {reg1}, {reg2}"), "FMvXD"); } TEST_F(AssemblerRISCV64Test, FMvWX) { - DriverStr(RepeatFR(&riscv64::Riscv64Assembler::FMvWX, "fmv.w.x {reg1}, {reg2}"), "FMvWX"); + DriverStr(RepeatFR(&Riscv64Assembler::FMvWX, "fmv.w.x {reg1}, {reg2}"), "FMvWX"); } TEST_F(AssemblerRISCV64Test, FMvDX) { - DriverStr(RepeatFR(&riscv64::Riscv64Assembler::FMvDX, "fmv.d.x {reg1}, {reg2}"), "FMvDX"); + DriverStr(RepeatFR(&Riscv64Assembler::FMvDX, "fmv.d.x {reg1}, {reg2}"), "FMvDX"); } TEST_F(AssemblerRISCV64Test, FClassS) { - DriverStr(RepeatRF(&riscv64::Riscv64Assembler::FClassS, "fclass.s {reg1}, {reg2}"), "FClassS"); + DriverStr(RepeatRF(&Riscv64Assembler::FClassS, "fclass.s {reg1}, {reg2}"), "FClassS"); } TEST_F(AssemblerRISCV64Test, FClassD) { - DriverStr(RepeatrF(&riscv64::Riscv64Assembler::FClassD, "fclass.d {reg1}, {reg2}"), "FClassD"); + DriverStr(RepeatrF(&Riscv64Assembler::FClassD, "fclass.d {reg1}, {reg2}"), "FClassD"); } // Pseudo instructions. @@ -2149,181 +2090,167 @@ TEST_F(AssemblerRISCV64Test, Li) { } TEST_F(AssemblerRISCV64Test, Mv) { - DriverStr(RepeatRR(&riscv64::Riscv64Assembler::Mv, "addi {reg1}, {reg2}, 0"), "Mv"); + DriverStr(RepeatRR(&Riscv64Assembler::Mv, "addi {reg1}, {reg2}, 0"), "Mv"); } TEST_F(AssemblerRISCV64Test, Not) { - DriverStr(RepeatRR(&riscv64::Riscv64Assembler::Not, "xori {reg1}, {reg2}, -1"), "Not"); + DriverStr(RepeatRR(&Riscv64Assembler::Not, "xori {reg1}, {reg2}, -1"), "Not"); } TEST_F(AssemblerRISCV64Test, Neg) { - DriverStr(RepeatRR(&riscv64::Riscv64Assembler::Neg, "sub {reg1}, x0, {reg2}"), "Neg"); + DriverStr(RepeatRR(&Riscv64Assembler::Neg, "sub {reg1}, x0, {reg2}"), "Neg"); } TEST_F(AssemblerRISCV64Test, NegW) { - DriverStr(RepeatRR(&riscv64::Riscv64Assembler::NegW, "subw {reg1}, x0, {reg2}"), "Neg"); + DriverStr(RepeatRR(&Riscv64Assembler::NegW, "subw {reg1}, x0, {reg2}"), "Neg"); } TEST_F(AssemblerRISCV64Test, SextB) { - DriverStr(RepeatRR(&riscv64::Riscv64Assembler::SextB, + DriverStr(RepeatRR(&Riscv64Assembler::SextB, "slli {reg1}, {reg2}, 56\n" "srai {reg1}, {reg1}, 56"), "SextB"); } TEST_F(AssemblerRISCV64Test, SextH) { - DriverStr(RepeatRR(&riscv64::Riscv64Assembler::SextH, + DriverStr(RepeatRR(&Riscv64Assembler::SextH, "slli {reg1}, {reg2}, 48\n" "srai {reg1}, {reg1}, 48"), "SextH"); } TEST_F(AssemblerRISCV64Test, SextW) { - DriverStr(RepeatRR(&riscv64::Riscv64Assembler::SextW, "addiw {reg1}, {reg2}, 0\n"), "SextW"); + DriverStr(RepeatRR(&Riscv64Assembler::SextW, "addiw {reg1}, {reg2}, 0\n"), "SextW"); } TEST_F(AssemblerRISCV64Test, ZextB) { - DriverStr(RepeatRR(&riscv64::Riscv64Assembler::ZextB, "andi {reg1}, {reg2}, 255"), "ZextB"); + DriverStr(RepeatRR(&Riscv64Assembler::ZextB, "andi {reg1}, {reg2}, 255"), "ZextB"); } TEST_F(AssemblerRISCV64Test, ZextH) { - DriverStr(RepeatRR(&riscv64::Riscv64Assembler::ZextH, + DriverStr(RepeatRR(&Riscv64Assembler::ZextH, "slli {reg1}, {reg2}, 48\n" "srli {reg1}, {reg1}, 48"), "SextH"); } TEST_F(AssemblerRISCV64Test, ZextW) { - DriverStr(RepeatRR(&riscv64::Riscv64Assembler::ZextW, + DriverStr(RepeatRR(&Riscv64Assembler::ZextW, "slli {reg1}, {reg2}, 32\n" "srli {reg1}, {reg1}, 32"), "SextW"); } TEST_F(AssemblerRISCV64Test, Seqz) { - DriverStr(RepeatRR(&riscv64::Riscv64Assembler::Seqz, "sltiu {reg1}, {reg2}, 1\n"), "Seqz"); + DriverStr(RepeatRR(&Riscv64Assembler::Seqz, "sltiu {reg1}, {reg2}, 1\n"), "Seqz"); } TEST_F(AssemblerRISCV64Test, Snez) { - DriverStr(RepeatRR(&riscv64::Riscv64Assembler::Snez, "sltu {reg1}, zero, {reg2}\n"), "Snez"); + DriverStr(RepeatRR(&Riscv64Assembler::Snez, "sltu {reg1}, zero, {reg2}\n"), "Snez"); } TEST_F(AssemblerRISCV64Test, Sltz) { - DriverStr(RepeatRR(&riscv64::Riscv64Assembler::Sltz, "slt {reg1}, {reg2}, zero\n"), "Sltz"); + DriverStr(RepeatRR(&Riscv64Assembler::Sltz, "slt {reg1}, {reg2}, zero\n"), "Sltz"); } TEST_F(AssemblerRISCV64Test, Sgtz) { - DriverStr(RepeatRR(&riscv64::Riscv64Assembler::Sgtz, "slt {reg1}, zero, {reg2}\n"), "Sgtz"); + DriverStr(RepeatRR(&Riscv64Assembler::Sgtz, "slt {reg1}, zero, {reg2}\n"), "Sgtz"); } TEST_F(AssemblerRISCV64Test, FMvS) { - DriverStr(RepeatFF(&riscv64::Riscv64Assembler::FMvS, "fsgnj.s {reg1}, {reg2}, {reg2}\n"), "FMvS"); + DriverStr(RepeatFF(&Riscv64Assembler::FMvS, "fsgnj.s {reg1}, {reg2}, {reg2}\n"), "FMvS"); } TEST_F(AssemblerRISCV64Test, FAbsS) { - DriverStr(RepeatFF(&riscv64::Riscv64Assembler::FAbsS, "fsgnjx.s {reg1}, {reg2}, {reg2}\n"), - "FAbsS"); + DriverStr(RepeatFF(&Riscv64Assembler::FAbsS, "fsgnjx.s {reg1}, {reg2}, {reg2}\n"), "FAbsS"); } TEST_F(AssemblerRISCV64Test, FNegS) { - DriverStr(RepeatFF(&riscv64::Riscv64Assembler::FNegS, "fsgnjn.s {reg1}, {reg2}, {reg2}\n"), - "FNegS"); + DriverStr(RepeatFF(&Riscv64Assembler::FNegS, "fsgnjn.s {reg1}, {reg2}, {reg2}\n"), "FNegS"); } TEST_F(AssemblerRISCV64Test, FMvD) { - DriverStr(RepeatFF(&riscv64::Riscv64Assembler::FMvD, "fsgnj.d {reg1}, {reg2}, {reg2}\n"), "FMvD"); + DriverStr(RepeatFF(&Riscv64Assembler::FMvD, "fsgnj.d {reg1}, {reg2}, {reg2}\n"), "FMvD"); } TEST_F(AssemblerRISCV64Test, FAbsD) { - DriverStr(RepeatFF(&riscv64::Riscv64Assembler::FAbsD, "fsgnjx.d {reg1}, {reg2}, {reg2}\n"), - "FAbsD"); + DriverStr(RepeatFF(&Riscv64Assembler::FAbsD, "fsgnjx.d {reg1}, {reg2}, {reg2}\n"), "FAbsD"); } TEST_F(AssemblerRISCV64Test, FNegD) { - DriverStr(RepeatFF(&riscv64::Riscv64Assembler::FNegD, "fsgnjn.d {reg1}, {reg2}, {reg2}\n"), - "FNegD"); + DriverStr(RepeatFF(&Riscv64Assembler::FNegD, "fsgnjn.d {reg1}, {reg2}, {reg2}\n"), "FNegD"); } TEST_F(AssemblerRISCV64Test, Beqz) { // TODO(riscv64): Change "-11, 2" to "-12, 1" for "C" Standard Extension. - DriverStr(RepeatRIbS(&riscv64::Riscv64Assembler::Beqz, -11, 2, "beq {reg}, zero, {imm}\n"), - "Beqz"); + DriverStr(RepeatRIbS(&Riscv64Assembler::Beqz, -11, 2, "beq {reg}, zero, {imm}\n"), "Beqz"); } TEST_F(AssemblerRISCV64Test, Bnez) { // TODO(riscv64): Change "-11, 2" to "-12, 1" for "C" Standard Extension. - DriverStr(RepeatRIbS(&riscv64::Riscv64Assembler::Bnez, -11, 2, "bne {reg}, zero, {imm}\n"), - "Bnez"); + DriverStr(RepeatRIbS(&Riscv64Assembler::Bnez, -11, 2, "bne {reg}, zero, {imm}\n"), "Bnez"); } TEST_F(AssemblerRISCV64Test, Blez) { // TODO(riscv64): Change "-11, 2" to "-12, 1" for "C" Standard Extension. - DriverStr(RepeatRIbS(&riscv64::Riscv64Assembler::Blez, -11, 2, "bge zero, {reg}, {imm}\n"), - "Blez"); + DriverStr(RepeatRIbS(&Riscv64Assembler::Blez, -11, 2, "bge zero, {reg}, {imm}\n"), "Blez"); } TEST_F(AssemblerRISCV64Test, Bgez) { // TODO(riscv64): Change "-11, 2" to "-12, 1" for "C" Standard Extension. - DriverStr(RepeatRIbS(&riscv64::Riscv64Assembler::Bgez, -11, 2, "bge {reg}, zero, {imm}\n"), - "Bgez"); + DriverStr(RepeatRIbS(&Riscv64Assembler::Bgez, -11, 2, "bge {reg}, zero, {imm}\n"), "Bgez"); } TEST_F(AssemblerRISCV64Test, Bltz) { // TODO(riscv64): Change "-11, 2" to "-12, 1" for "C" Standard Extension. - DriverStr(RepeatRIbS(&riscv64::Riscv64Assembler::Bltz, -11, 2, "blt {reg}, zero, {imm}\n"), - "Bltz"); + DriverStr(RepeatRIbS(&Riscv64Assembler::Bltz, -11, 2, "blt {reg}, zero, {imm}\n"), "Bltz"); } TEST_F(AssemblerRISCV64Test, Bgtz) { // TODO(riscv64): Change "-11, 2" to "-12, 1" for "C" Standard Extension. - DriverStr(RepeatRIbS(&riscv64::Riscv64Assembler::Bgtz, -11, 2, "blt zero, {reg}, {imm}\n"), - "Bgtz"); + DriverStr(RepeatRIbS(&Riscv64Assembler::Bgtz, -11, 2, "blt zero, {reg}, {imm}\n"), "Bgtz"); } TEST_F(AssemblerRISCV64Test, Bgt) { // TODO(riscv64): Change "-11, 2" to "-12, 1" for "C" Standard Extension. - DriverStr(RepeatRRIbS(&riscv64::Riscv64Assembler::Bgt, -11, 2, "blt {reg2}, {reg1}, {imm}\n"), - "Bgt"); + DriverStr(RepeatRRIbS(&Riscv64Assembler::Bgt, -11, 2, "blt {reg2}, {reg1}, {imm}\n"), "Bgt"); } TEST_F(AssemblerRISCV64Test, Ble) { // TODO(riscv64): Change "-11, 2" to "-12, 1" for "C" Standard Extension. - DriverStr(RepeatRRIbS(&riscv64::Riscv64Assembler::Ble, -11, 2, "bge {reg2}, {reg1}, {imm}\n"), - "Bge"); + DriverStr(RepeatRRIbS(&Riscv64Assembler::Ble, -11, 2, "bge {reg2}, {reg1}, {imm}\n"), "Bge"); } TEST_F(AssemblerRISCV64Test, Bgtu) { // TODO(riscv64): Change "-11, 2" to "-12, 1" for "C" Standard Extension. - DriverStr(RepeatRRIbS(&riscv64::Riscv64Assembler::Bgtu, -11, 2, "bltu {reg2}, {reg1}, {imm}\n"), - "Bgtu"); + DriverStr(RepeatRRIbS(&Riscv64Assembler::Bgtu, -11, 2, "bltu {reg2}, {reg1}, {imm}\n"), "Bgtu"); } TEST_F(AssemblerRISCV64Test, Bleu) { // TODO(riscv64): Change "-11, 2" to "-12, 1" for "C" Standard Extension. - DriverStr(RepeatRRIbS(&riscv64::Riscv64Assembler::Bleu, -11, 2, "bgeu {reg2}, {reg1}, {imm}\n"), - "Bgeu"); + DriverStr(RepeatRRIbS(&Riscv64Assembler::Bleu, -11, 2, "bgeu {reg2}, {reg1}, {imm}\n"), "Bgeu"); } TEST_F(AssemblerRISCV64Test, J) { // TODO(riscv64): Change "-19, 2" to "-20, 1" for "C" Standard Extension. - DriverStr(RepeatIbS<int32_t>(&riscv64::Riscv64Assembler::J, -19, 2, "j {imm}\n"), "J"); + DriverStr(RepeatIbS<int32_t>(&Riscv64Assembler::J, -19, 2, "j {imm}\n"), "J"); } TEST_F(AssemblerRISCV64Test, JalRA) { // TODO(riscv64): Change "-19, 2" to "-20, 1" for "C" Standard Extension. - DriverStr(RepeatIbS<int32_t>(&riscv64::Riscv64Assembler::Jal, -19, 2, "jal {imm}\n"), "JalRA"); + DriverStr(RepeatIbS<int32_t>(&Riscv64Assembler::Jal, -19, 2, "jal {imm}\n"), "JalRA"); } TEST_F(AssemblerRISCV64Test, Jr) { - DriverStr(RepeatR(&riscv64::Riscv64Assembler::Jr, "jr {reg}\n"), "Jr"); + DriverStr(RepeatR(&Riscv64Assembler::Jr, "jr {reg}\n"), "Jr"); } TEST_F(AssemblerRISCV64Test, JalrRA) { - DriverStr(RepeatR(&riscv64::Riscv64Assembler::Jalr, "jalr {reg}\n"), "JalrRA"); + DriverStr(RepeatR(&Riscv64Assembler::Jalr, "jalr {reg}\n"), "JalrRA"); } TEST_F(AssemblerRISCV64Test, Jalr0) { - DriverStr(RepeatRR(&riscv64::Riscv64Assembler::Jalr, "jalr {reg1}, {reg2}\n"), "Jalr0"); + DriverStr(RepeatRR(&Riscv64Assembler::Jalr, "jalr {reg1}, {reg2}\n"), "Jalr0"); } TEST_F(AssemblerRISCV64Test, Ret) { @@ -2332,15 +2259,15 @@ TEST_F(AssemblerRISCV64Test, Ret) { } TEST_F(AssemblerRISCV64Test, RdCycle) { - DriverStr(RepeatR(&riscv64::Riscv64Assembler::RdCycle, "rdcycle {reg}\n"), "RdCycle"); + DriverStr(RepeatR(&Riscv64Assembler::RdCycle, "rdcycle {reg}\n"), "RdCycle"); } TEST_F(AssemblerRISCV64Test, RdTime) { - DriverStr(RepeatR(&riscv64::Riscv64Assembler::RdTime, "rdtime {reg}\n"), "RdTime"); + DriverStr(RepeatR(&Riscv64Assembler::RdTime, "rdtime {reg}\n"), "RdTime"); } TEST_F(AssemblerRISCV64Test, RdInstret) { - DriverStr(RepeatR(&riscv64::Riscv64Assembler::RdInstret, "rdinstret {reg}\n"), "RdInstret"); + DriverStr(RepeatR(&Riscv64Assembler::RdInstret, "rdinstret {reg}\n"), "RdInstret"); } TEST_F(AssemblerRISCV64Test, Csrr) { @@ -2499,12 +2426,12 @@ TEST_F(AssemblerRISCV64Test, BcondElimination) { Riscv64Label label; __ Bind(&label); __ Nop(); - for (XRegister* reg : GetRegisters()) { - __ Bne(*reg, *reg, &label); - __ Blt(*reg, *reg, &label); - __ Bgt(*reg, *reg, &label); - __ Bltu(*reg, *reg, &label); - __ Bgtu(*reg, *reg, &label); + for (XRegister reg : GetRegisters()) { + __ Bne(reg, reg, &label); + __ Blt(reg, reg, &label); + __ Bgt(reg, reg, &label); + __ Bltu(reg, reg, &label); + __ Bgtu(reg, reg, &label); } DriverStr("nop\n", "BcondElimination"); } @@ -2513,12 +2440,12 @@ TEST_F(AssemblerRISCV64Test, BcondUnconditional) { Riscv64Label label; __ Bind(&label); __ Nop(); - for (XRegister* reg : GetRegisters()) { - __ Beq(*reg, *reg, &label); - __ Bge(*reg, *reg, &label); - __ Ble(*reg, *reg, &label); - __ Bleu(*reg, *reg, &label); - __ Bgeu(*reg, *reg, &label); + for (XRegister reg : GetRegisters()) { + __ Beq(reg, reg, &label); + __ Bge(reg, reg, &label); + __ Ble(reg, reg, &label); + __ Bleu(reg, reg, &label); + __ Bgeu(reg, reg, &label); } std::string expected = "1:\n" diff --git a/compiler/utils/x86/assembler_x86_test.cc b/compiler/utils/x86/assembler_x86_test.cc index 5da6f04402..36a67b0535 100644 --- a/compiler/utils/x86/assembler_x86_test.cc +++ b/compiler/utils/x86/assembler_x86_test.cc @@ -89,19 +89,7 @@ class AssemblerX86Test : public AssemblerTest<x86::X86Assembler, addresses_.push_back(x86::Address(x86::ESP, 987654321)); } - if (registers_.size() == 0) { - registers_.insert(end(registers_), - { - new x86::Register(x86::EAX), - new x86::Register(x86::EBX), - new x86::Register(x86::ECX), - new x86::Register(x86::EDX), - new x86::Register(x86::EBP), - new x86::Register(x86::ESP), - new x86::Register(x86::ESI), - new x86::Register(x86::EDI) - }); - + if (secondary_register_names_.empty()) { secondary_register_names_.emplace(x86::Register(x86::EAX), "ax"); secondary_register_names_.emplace(x86::Register(x86::EBX), "bx"); secondary_register_names_.emplace(x86::Register(x86::ECX), "cx"); @@ -121,38 +109,28 @@ class AssemblerX86Test : public AssemblerTest<x86::X86Assembler, tertiary_register_names_.emplace(x86::Register(x86::ESI), "dh"); tertiary_register_names_.emplace(x86::Register(x86::EDI), "bh"); } - - if (fp_registers_.size() == 0) { - fp_registers_.insert(end(fp_registers_), - { - new x86::XmmRegister(x86::XMM0), - new x86::XmmRegister(x86::XMM1), - new x86::XmmRegister(x86::XMM2), - new x86::XmmRegister(x86::XMM3), - new x86::XmmRegister(x86::XMM4), - new x86::XmmRegister(x86::XMM5), - new x86::XmmRegister(x86::XMM6), - new x86::XmmRegister(x86::XMM7) - }); - } } void TearDown() override { AssemblerTest::TearDown(); - STLDeleteElements(®isters_); - STLDeleteElements(&fp_registers_); } std::vector<x86::Address> GetAddresses() override { return addresses_; } - std::vector<x86::Register*> GetRegisters() override { - return registers_; + ArrayRef<const x86::Register> GetRegisters() override { + static constexpr x86::Register kRegisters[] = { + x86::EAX, x86::EBX, x86::ECX, x86::EDX, x86::EBP, x86::ESP, x86::ESI, x86::EDI + }; + return ArrayRef<const x86::Register>(kRegisters); } - std::vector<x86::XmmRegister*> GetFPRegisters() override { - return fp_registers_; + ArrayRef<const x86::XmmRegister> GetFPRegisters() override { + static constexpr x86::XmmRegister kFPRegisters[] = { + x86::XMM0, x86::XMM1, x86::XMM2, x86::XMM3, x86::XMM4, x86::XMM5, x86::XMM6, x86::XMM7 + }; + return ArrayRef<const x86::XmmRegister>(kFPRegisters); } x86::Immediate CreateImmediate(int64_t imm_value) override { @@ -173,10 +151,10 @@ class AssemblerX86Test : public AssemblerTest<x86::X86Assembler, private: std::vector<x86::Address> addresses_; - std::vector<x86::Register*> registers_; + std::vector<x86::Register> registers_; std::map<x86::Register, std::string, X86RegisterCompare> secondary_register_names_; std::map<x86::Register, std::string, X86RegisterCompare> tertiary_register_names_; - std::vector<x86::XmmRegister*> fp_registers_; + std::vector<x86::XmmRegister> fp_registers_; }; class AssemblerX86AVXTest : public AssemblerX86Test { @@ -267,28 +245,28 @@ TEST_F(AssemblerX86Test, RepeatAF) { TEST_F(AssemblerX86Test, PoplAllAddresses) { // Make sure all addressing modes combinations are tested at least once. std::vector<x86::Address> all_addresses; - for (x86::Register* base : GetRegisters()) { + for (x86::Register base : GetRegisters()) { // Base only. - all_addresses.push_back(x86::Address(*base, -1)); - all_addresses.push_back(x86::Address(*base, 0)); - all_addresses.push_back(x86::Address(*base, 1)); - all_addresses.push_back(x86::Address(*base, 123456789)); - for (x86::Register* index : GetRegisters()) { - if (*index == x86::ESP) { + all_addresses.push_back(x86::Address(base, -1)); + all_addresses.push_back(x86::Address(base, 0)); + all_addresses.push_back(x86::Address(base, 1)); + all_addresses.push_back(x86::Address(base, 123456789)); + for (x86::Register index : GetRegisters()) { + if (index == x86::ESP) { // Index cannot be ESP. continue; - } else if (*base == *index) { + } else if (base == index) { // Index only. - all_addresses.push_back(x86::Address(*index, TIMES_1, -1)); - all_addresses.push_back(x86::Address(*index, TIMES_2, 0)); - all_addresses.push_back(x86::Address(*index, TIMES_4, 1)); - all_addresses.push_back(x86::Address(*index, TIMES_8, 123456789)); + all_addresses.push_back(x86::Address(index, TIMES_1, -1)); + all_addresses.push_back(x86::Address(index, TIMES_2, 0)); + all_addresses.push_back(x86::Address(index, TIMES_4, 1)); + all_addresses.push_back(x86::Address(index, TIMES_8, 123456789)); } // Base and index. - all_addresses.push_back(x86::Address(*base, *index, TIMES_1, -1)); - all_addresses.push_back(x86::Address(*base, *index, TIMES_2, 0)); - all_addresses.push_back(x86::Address(*base, *index, TIMES_4, 1)); - all_addresses.push_back(x86::Address(*base, *index, TIMES_8, 123456789)); + all_addresses.push_back(x86::Address(base, index, TIMES_1, -1)); + all_addresses.push_back(x86::Address(base, index, TIMES_2, 0)); + all_addresses.push_back(x86::Address(base, index, TIMES_4, 1)); + all_addresses.push_back(x86::Address(base, index, TIMES_8, 123456789)); } } DriverStr(RepeatA(&x86::X86Assembler::popl, all_addresses, "popl {mem}"), "popq"); @@ -510,11 +488,11 @@ TEST_F(AssemblerX86Test, PopcntlAddress) { // Rorl only allows CL as the shift count. std::string rorl_fn(AssemblerX86Test::Base* assembler_test, x86::X86Assembler* assembler) { std::ostringstream str; - std::vector<x86::Register*> registers = assembler_test->GetRegisters(); + ArrayRef<const x86::Register> registers = assembler_test->GetRegisters(); x86::Register shifter(x86::ECX); - for (auto reg : registers) { - assembler->rorl(*reg, shifter); - str << "rorl %cl, %" << assembler_test->GetRegisterName(*reg) << "\n"; + for (auto&& reg : registers) { + assembler->rorl(reg, shifter); + str << "rorl %cl, %" << assembler_test->GetRegisterName(reg) << "\n"; } return str.str(); } @@ -530,11 +508,11 @@ TEST_F(AssemblerX86Test, RorlImm) { // Roll only allows CL as the shift count. std::string roll_fn(AssemblerX86Test::Base* assembler_test, x86::X86Assembler* assembler) { std::ostringstream str; - std::vector<x86::Register*> registers = assembler_test->GetRegisters(); + ArrayRef<const x86::Register> registers = assembler_test->GetRegisters(); x86::Register shifter(x86::ECX); - for (auto reg : registers) { - assembler->roll(*reg, shifter); - str << "roll %cl, %" << assembler_test->GetRegisterName(*reg) << "\n"; + for (auto&& reg : registers) { + assembler->roll(reg, shifter); + str << "roll %cl, %" << assembler_test->GetRegisterName(reg) << "\n"; } return str.str(); } @@ -1379,27 +1357,27 @@ TEST_F(AssemblerX86Test, AddressDisplaceBy) { for (int32_t disp0 : displacements) { // initial displacement for (int32_t disp : displacements) { // extra displacement - for (const x86::Register *reg : GetRegisters()) { + for (x86::Register reg : GetRegisters()) { // Test non-SIB addressing. - EXPECT_EQ(x86::Address::displace(x86::Address(*reg, disp0), disp), - x86::Address(*reg, disp0 + disp)); + EXPECT_EQ(x86::Address::displace(x86::Address(reg, disp0), disp), + x86::Address(reg, disp0 + disp)); // Test SIB addressing with EBP base. - if (*reg != x86::ESP) { + if (reg != x86::ESP) { for (ScaleFactor scale : scales) { - EXPECT_EQ(x86::Address::displace(x86::Address(*reg, scale, disp0), disp), - x86::Address(*reg, scale, disp0 + disp)); + EXPECT_EQ(x86::Address::displace(x86::Address(reg, scale, disp0), disp), + x86::Address(reg, scale, disp0 + disp)); } } // Test SIB addressing with different base. - for (const x86::Register *index : GetRegisters()) { - if (*index == x86::ESP) { + for (x86::Register index : GetRegisters()) { + if (index == x86::ESP) { continue; // Skip ESP as it cannot be used with this address constructor. } for (ScaleFactor scale : scales) { - EXPECT_EQ(x86::Address::displace(x86::Address(*reg, *index, scale, disp0), disp), - x86::Address(*reg, *index, scale, disp0 + disp)); + EXPECT_EQ(x86::Address::displace(x86::Address(reg, index, scale, disp0), disp), + x86::Address(reg, index, scale, disp0 + disp)); } } diff --git a/compiler/utils/x86_64/assembler_x86_64_test.cc b/compiler/utils/x86_64/assembler_x86_64_test.cc index 5f7845f02c..e985441101 100644 --- a/compiler/utils/x86_64/assembler_x86_64_test.cc +++ b/compiler/utils/x86_64/assembler_x86_64_test.cc @@ -199,24 +199,7 @@ class AssemblerX86_64Test : public AssemblerTest<x86_64::X86_64Assembler, addresses_.push_back(x86_64::Address(x86_64::CpuRegister(x86_64::R15), 123456789)); } - if (registers_.size() == 0) { - registers_.push_back(new x86_64::CpuRegister(x86_64::RAX)); - registers_.push_back(new x86_64::CpuRegister(x86_64::RBX)); - registers_.push_back(new x86_64::CpuRegister(x86_64::RCX)); - registers_.push_back(new x86_64::CpuRegister(x86_64::RDX)); - registers_.push_back(new x86_64::CpuRegister(x86_64::RBP)); - registers_.push_back(new x86_64::CpuRegister(x86_64::RSP)); - registers_.push_back(new x86_64::CpuRegister(x86_64::RSI)); - registers_.push_back(new x86_64::CpuRegister(x86_64::RDI)); - registers_.push_back(new x86_64::CpuRegister(x86_64::R8)); - registers_.push_back(new x86_64::CpuRegister(x86_64::R9)); - registers_.push_back(new x86_64::CpuRegister(x86_64::R10)); - registers_.push_back(new x86_64::CpuRegister(x86_64::R11)); - registers_.push_back(new x86_64::CpuRegister(x86_64::R12)); - registers_.push_back(new x86_64::CpuRegister(x86_64::R13)); - registers_.push_back(new x86_64::CpuRegister(x86_64::R14)); - registers_.push_back(new x86_64::CpuRegister(x86_64::R15)); - + if (secondary_register_names_.empty()) { secondary_register_names_.emplace(x86_64::CpuRegister(x86_64::RAX), "eax"); secondary_register_names_.emplace(x86_64::CpuRegister(x86_64::RBX), "ebx"); secondary_register_names_.emplace(x86_64::CpuRegister(x86_64::RCX), "ecx"); @@ -267,42 +250,59 @@ class AssemblerX86_64Test : public AssemblerTest<x86_64::X86_64Assembler, quaternary_register_names_.emplace(x86_64::CpuRegister(x86_64::R13), "r13b"); quaternary_register_names_.emplace(x86_64::CpuRegister(x86_64::R14), "r14b"); quaternary_register_names_.emplace(x86_64::CpuRegister(x86_64::R15), "r15b"); - - fp_registers_.push_back(new x86_64::XmmRegister(x86_64::XMM0)); - fp_registers_.push_back(new x86_64::XmmRegister(x86_64::XMM1)); - fp_registers_.push_back(new x86_64::XmmRegister(x86_64::XMM2)); - fp_registers_.push_back(new x86_64::XmmRegister(x86_64::XMM3)); - fp_registers_.push_back(new x86_64::XmmRegister(x86_64::XMM4)); - fp_registers_.push_back(new x86_64::XmmRegister(x86_64::XMM5)); - fp_registers_.push_back(new x86_64::XmmRegister(x86_64::XMM6)); - fp_registers_.push_back(new x86_64::XmmRegister(x86_64::XMM7)); - fp_registers_.push_back(new x86_64::XmmRegister(x86_64::XMM8)); - fp_registers_.push_back(new x86_64::XmmRegister(x86_64::XMM9)); - fp_registers_.push_back(new x86_64::XmmRegister(x86_64::XMM10)); - fp_registers_.push_back(new x86_64::XmmRegister(x86_64::XMM11)); - fp_registers_.push_back(new x86_64::XmmRegister(x86_64::XMM12)); - fp_registers_.push_back(new x86_64::XmmRegister(x86_64::XMM13)); - fp_registers_.push_back(new x86_64::XmmRegister(x86_64::XMM14)); - fp_registers_.push_back(new x86_64::XmmRegister(x86_64::XMM15)); } } void TearDown() override { AssemblerTest::TearDown(); - STLDeleteElements(®isters_); - STLDeleteElements(&fp_registers_); } std::vector<x86_64::Address> GetAddresses() override { return addresses_; } - std::vector<x86_64::CpuRegister*> GetRegisters() override { - return registers_; + ArrayRef<const x86_64::CpuRegister> GetRegisters() override { + static constexpr x86_64::CpuRegister kRegisters[] = { + x86_64::CpuRegister(x86_64::RAX), + x86_64::CpuRegister(x86_64::RBX), + x86_64::CpuRegister(x86_64::RCX), + x86_64::CpuRegister(x86_64::RDX), + x86_64::CpuRegister(x86_64::RBP), + x86_64::CpuRegister(x86_64::RSP), + x86_64::CpuRegister(x86_64::RSI), + x86_64::CpuRegister(x86_64::RDI), + x86_64::CpuRegister(x86_64::R8), + x86_64::CpuRegister(x86_64::R9), + x86_64::CpuRegister(x86_64::R10), + x86_64::CpuRegister(x86_64::R11), + x86_64::CpuRegister(x86_64::R12), + x86_64::CpuRegister(x86_64::R13), + x86_64::CpuRegister(x86_64::R14), + x86_64::CpuRegister(x86_64::R15), + }; + return ArrayRef<const x86_64::CpuRegister>(kRegisters); } - std::vector<x86_64::XmmRegister*> GetFPRegisters() override { - return fp_registers_; + ArrayRef<const x86_64::XmmRegister> GetFPRegisters() override { + static constexpr x86_64::XmmRegister kFPRegisters[] = { + x86_64::XmmRegister(x86_64::XMM0), + x86_64::XmmRegister(x86_64::XMM1), + x86_64::XmmRegister(x86_64::XMM2), + x86_64::XmmRegister(x86_64::XMM3), + x86_64::XmmRegister(x86_64::XMM4), + x86_64::XmmRegister(x86_64::XMM5), + x86_64::XmmRegister(x86_64::XMM6), + x86_64::XmmRegister(x86_64::XMM7), + x86_64::XmmRegister(x86_64::XMM8), + x86_64::XmmRegister(x86_64::XMM9), + x86_64::XmmRegister(x86_64::XMM10), + x86_64::XmmRegister(x86_64::XMM11), + x86_64::XmmRegister(x86_64::XMM12), + x86_64::XmmRegister(x86_64::XMM13), + x86_64::XmmRegister(x86_64::XMM14), + x86_64::XmmRegister(x86_64::XMM15), + }; + return ArrayRef<const x86_64::XmmRegister>(kFPRegisters); } x86_64::Immediate CreateImmediate(int64_t imm_value) override { @@ -328,11 +328,9 @@ class AssemblerX86_64Test : public AssemblerTest<x86_64::X86_64Assembler, private: std::vector<x86_64::Address> addresses_; - std::vector<x86_64::CpuRegister*> registers_; std::map<x86_64::CpuRegister, std::string, X86_64CpuRegisterCompare> secondary_register_names_; std::map<x86_64::CpuRegister, std::string, X86_64CpuRegisterCompare> tertiary_register_names_; std::map<x86_64::CpuRegister, std::string, X86_64CpuRegisterCompare> quaternary_register_names_; - std::vector<x86_64::XmmRegister*> fp_registers_; }; class AssemblerX86_64AVXTest : public AssemblerX86_64Test { @@ -515,28 +513,28 @@ TEST_F(AssemblerX86_64Test, Toolchain) { TEST_F(AssemblerX86_64Test, PopqAllAddresses) { // Make sure all addressing modes combinations are tested at least once. std::vector<x86_64::Address> all_addresses; - for (x86_64::CpuRegister* base : GetRegisters()) { + for (const x86_64::CpuRegister& base : GetRegisters()) { // Base only. - all_addresses.push_back(x86_64::Address(*base, -1)); - all_addresses.push_back(x86_64::Address(*base, 0)); - all_addresses.push_back(x86_64::Address(*base, 1)); - all_addresses.push_back(x86_64::Address(*base, 123456789)); - for (x86_64::CpuRegister* index : GetRegisters()) { - if (index->AsRegister() == x86_64::RSP) { + all_addresses.push_back(x86_64::Address(base, -1)); + all_addresses.push_back(x86_64::Address(base, 0)); + all_addresses.push_back(x86_64::Address(base, 1)); + all_addresses.push_back(x86_64::Address(base, 123456789)); + for (const x86_64::CpuRegister& index : GetRegisters()) { + if (index.AsRegister() == x86_64::RSP) { // Index cannot be RSP. continue; - } else if (base->AsRegister() == index->AsRegister()) { + } else if (base.AsRegister() == index.AsRegister()) { // Index only. - all_addresses.push_back(x86_64::Address(*index, TIMES_1, -1)); - all_addresses.push_back(x86_64::Address(*index, TIMES_2, 0)); - all_addresses.push_back(x86_64::Address(*index, TIMES_4, 1)); - all_addresses.push_back(x86_64::Address(*index, TIMES_8, 123456789)); + all_addresses.push_back(x86_64::Address(index, TIMES_1, -1)); + all_addresses.push_back(x86_64::Address(index, TIMES_2, 0)); + all_addresses.push_back(x86_64::Address(index, TIMES_4, 1)); + all_addresses.push_back(x86_64::Address(index, TIMES_8, 123456789)); } // Base and index. - all_addresses.push_back(x86_64::Address(*base, *index, TIMES_1, -1)); - all_addresses.push_back(x86_64::Address(*base, *index, TIMES_2, 0)); - all_addresses.push_back(x86_64::Address(*base, *index, TIMES_4, 1)); - all_addresses.push_back(x86_64::Address(*base, *index, TIMES_8, 123456789)); + all_addresses.push_back(x86_64::Address(base, index, TIMES_1, -1)); + all_addresses.push_back(x86_64::Address(base, index, TIMES_2, 0)); + all_addresses.push_back(x86_64::Address(base, index, TIMES_4, 1)); + all_addresses.push_back(x86_64::Address(base, index, TIMES_8, 123456789)); } } DriverStr(RepeatA(&x86_64::X86_64Assembler::popq, all_addresses, "popq {mem}"), "popq"); @@ -641,11 +639,11 @@ TEST_F(AssemblerX86_64Test, SublImm) { // Shll only allows CL as the shift count. std::string shll_fn(AssemblerX86_64Test::Base* assembler_test, x86_64::X86_64Assembler* assembler) { std::ostringstream str; - std::vector<x86_64::CpuRegister*> registers = assembler_test->GetRegisters(); + ArrayRef<const x86_64::CpuRegister> registers = assembler_test->GetRegisters(); x86_64::CpuRegister shifter(x86_64::RCX); - for (auto reg : registers) { - assembler->shll(*reg, shifter); - str << "shll %cl, %" << assembler_test->GetSecondaryRegisterName(*reg) << "\n"; + for (auto&& reg : registers) { + assembler->shll(reg, shifter); + str << "shll %cl, %" << assembler_test->GetSecondaryRegisterName(reg) << "\n"; } return str.str(); } @@ -662,11 +660,11 @@ TEST_F(AssemblerX86_64Test, ShllImm) { // Shlq only allows CL as the shift count. std::string shlq_fn(AssemblerX86_64Test::Base* assembler_test, x86_64::X86_64Assembler* assembler) { std::ostringstream str; - std::vector<x86_64::CpuRegister*> registers = assembler_test->GetRegisters(); + ArrayRef<const x86_64::CpuRegister> registers = assembler_test->GetRegisters(); x86_64::CpuRegister shifter(x86_64::RCX); - for (auto reg : registers) { - assembler->shlq(*reg, shifter); - str << "shlq %cl, %" << assembler_test->GetRegisterName(*reg) << "\n"; + for (auto&& reg : registers) { + assembler->shlq(reg, shifter); + str << "shlq %cl, %" << assembler_test->GetRegisterName(reg) << "\n"; } return str.str(); } @@ -683,11 +681,11 @@ TEST_F(AssemblerX86_64Test, ShlqImm) { // Shrl only allows CL as the shift count. std::string shrl_fn(AssemblerX86_64Test::Base* assembler_test, x86_64::X86_64Assembler* assembler) { std::ostringstream str; - std::vector<x86_64::CpuRegister*> registers = assembler_test->GetRegisters(); + ArrayRef<const x86_64::CpuRegister> registers = assembler_test->GetRegisters(); x86_64::CpuRegister shifter(x86_64::RCX); - for (auto reg : registers) { - assembler->shrl(*reg, shifter); - str << "shrl %cl, %" << assembler_test->GetSecondaryRegisterName(*reg) << "\n"; + for (auto&& reg : registers) { + assembler->shrl(reg, shifter); + str << "shrl %cl, %" << assembler_test->GetSecondaryRegisterName(reg) << "\n"; } return str.str(); } @@ -703,11 +701,11 @@ TEST_F(AssemblerX86_64Test, ShrlImm) { // Shrq only allows CL as the shift count. std::string shrq_fn(AssemblerX86_64Test::Base* assembler_test, x86_64::X86_64Assembler* assembler) { std::ostringstream str; - std::vector<x86_64::CpuRegister*> registers = assembler_test->GetRegisters(); + ArrayRef<const x86_64::CpuRegister> registers = assembler_test->GetRegisters(); x86_64::CpuRegister shifter(x86_64::RCX); - for (auto reg : registers) { - assembler->shrq(*reg, shifter); - str << "shrq %cl, %" << assembler_test->GetRegisterName(*reg) << "\n"; + for (auto&& reg : registers) { + assembler->shrq(reg, shifter); + str << "shrq %cl, %" << assembler_test->GetRegisterName(reg) << "\n"; } return str.str(); } @@ -723,11 +721,11 @@ TEST_F(AssemblerX86_64Test, ShrqImm) { // Sarl only allows CL as the shift count. std::string sarl_fn(AssemblerX86_64Test::Base* assembler_test, x86_64::X86_64Assembler* assembler) { std::ostringstream str; - std::vector<x86_64::CpuRegister*> registers = assembler_test->GetRegisters(); + ArrayRef<const x86_64::CpuRegister> registers = assembler_test->GetRegisters(); x86_64::CpuRegister shifter(x86_64::RCX); - for (auto reg : registers) { - assembler->sarl(*reg, shifter); - str << "sarl %cl, %" << assembler_test->GetSecondaryRegisterName(*reg) << "\n"; + for (auto&& reg : registers) { + assembler->sarl(reg, shifter); + str << "sarl %cl, %" << assembler_test->GetSecondaryRegisterName(reg) << "\n"; } return str.str(); } @@ -743,11 +741,11 @@ TEST_F(AssemblerX86_64Test, SarlImm) { // Sarq only allows CL as the shift count. std::string sarq_fn(AssemblerX86_64Test::Base* assembler_test, x86_64::X86_64Assembler* assembler) { std::ostringstream str; - std::vector<x86_64::CpuRegister*> registers = assembler_test->GetRegisters(); + ArrayRef<const x86_64::CpuRegister> registers = assembler_test->GetRegisters(); x86_64::CpuRegister shifter(x86_64::RCX); - for (auto reg : registers) { - assembler->sarq(*reg, shifter); - str << "sarq %cl, %" << assembler_test->GetRegisterName(*reg) << "\n"; + for (auto&& reg : registers) { + assembler->sarq(reg, shifter); + str << "sarq %cl, %" << assembler_test->GetRegisterName(reg) << "\n"; } return str.str(); } @@ -763,11 +761,11 @@ TEST_F(AssemblerX86_64Test, SarqImm) { // Rorl only allows CL as the shift count. std::string rorl_fn(AssemblerX86_64Test::Base* assembler_test, x86_64::X86_64Assembler* assembler) { std::ostringstream str; - std::vector<x86_64::CpuRegister*> registers = assembler_test->GetRegisters(); + ArrayRef<const x86_64::CpuRegister> registers = assembler_test->GetRegisters(); x86_64::CpuRegister shifter(x86_64::RCX); - for (auto reg : registers) { - assembler->rorl(*reg, shifter); - str << "rorl %cl, %" << assembler_test->GetSecondaryRegisterName(*reg) << "\n"; + for (auto&& reg : registers) { + assembler->rorl(reg, shifter); + str << "rorl %cl, %" << assembler_test->GetSecondaryRegisterName(reg) << "\n"; } return str.str(); } @@ -783,11 +781,11 @@ TEST_F(AssemblerX86_64Test, RorlImm) { // Roll only allows CL as the shift count. std::string roll_fn(AssemblerX86_64Test::Base* assembler_test, x86_64::X86_64Assembler* assembler) { std::ostringstream str; - std::vector<x86_64::CpuRegister*> registers = assembler_test->GetRegisters(); + ArrayRef<const x86_64::CpuRegister> registers = assembler_test->GetRegisters(); x86_64::CpuRegister shifter(x86_64::RCX); - for (auto reg : registers) { - assembler->roll(*reg, shifter); - str << "roll %cl, %" << assembler_test->GetSecondaryRegisterName(*reg) << "\n"; + for (auto&& reg : registers) { + assembler->roll(reg, shifter); + str << "roll %cl, %" << assembler_test->GetSecondaryRegisterName(reg) << "\n"; } return str.str(); } @@ -803,11 +801,11 @@ TEST_F(AssemblerX86_64Test, RollImm) { // Rorq only allows CL as the shift count. std::string rorq_fn(AssemblerX86_64Test::Base* assembler_test, x86_64::X86_64Assembler* assembler) { std::ostringstream str; - std::vector<x86_64::CpuRegister*> registers = assembler_test->GetRegisters(); + ArrayRef<const x86_64::CpuRegister> registers = assembler_test->GetRegisters(); x86_64::CpuRegister shifter(x86_64::RCX); - for (auto reg : registers) { - assembler->rorq(*reg, shifter); - str << "rorq %cl, %" << assembler_test->GetRegisterName(*reg) << "\n"; + for (auto&& reg : registers) { + assembler->rorq(reg, shifter); + str << "rorq %cl, %" << assembler_test->GetRegisterName(reg) << "\n"; } return str.str(); } @@ -823,11 +821,11 @@ TEST_F(AssemblerX86_64Test, RorqImm) { // Rolq only allows CL as the shift count. std::string rolq_fn(AssemblerX86_64Test::Base* assembler_test, x86_64::X86_64Assembler* assembler) { std::ostringstream str; - std::vector<x86_64::CpuRegister*> registers = assembler_test->GetRegisters(); + ArrayRef<const x86_64::CpuRegister> registers = assembler_test->GetRegisters(); x86_64::CpuRegister shifter(x86_64::RCX); - for (auto reg : registers) { - assembler->rolq(*reg, shifter); - str << "rolq %cl, %" << assembler_test->GetRegisterName(*reg) << "\n"; + for (auto&& reg : registers) { + assembler->rolq(reg, shifter); + str << "rolq %cl, %" << assembler_test->GetRegisterName(reg) << "\n"; } return str.str(); } @@ -2375,13 +2373,13 @@ std::string setcc_test_fn(AssemblerX86_64Test::Base* assembler_test, std::string suffixes[15] = { "o", "no", "b", "ae", "e", "ne", "be", "a", "s", "ns", "pe", "po", "l", "ge", "le" }; - std::vector<x86_64::CpuRegister*> registers = assembler_test->GetRegisters(); + ArrayRef<const x86_64::CpuRegister> registers = assembler_test->GetRegisters(); std::ostringstream str; - for (auto reg : registers) { + for (auto&& reg : registers) { for (size_t i = 0; i < 15; ++i) { - assembler->setcc(static_cast<x86_64::Condition>(i), *reg); - str << "set" << suffixes[i] << " %" << assembler_test->GetQuaternaryRegisterName(*reg) << "\n"; + assembler->setcc(static_cast<x86_64::Condition>(i), reg); + str << "set" << suffixes[i] << " %" << assembler_test->GetQuaternaryRegisterName(reg) << "\n"; } } @@ -2459,27 +2457,27 @@ TEST_F(AssemblerX86_64Test, AddressDisplaceBy) { for (int32_t disp0 : displacements) { // initial displacement for (int32_t disp : displacements) { // extra displacement - for (const x86_64::CpuRegister* reg : GetRegisters()) { + for (const x86_64::CpuRegister reg : GetRegisters()) { // Test non-SIB addressing. - EXPECT_EQ(x86_64::Address::displace(x86_64::Address(*reg, disp0), disp), - x86_64::Address(*reg, disp0 + disp)); + EXPECT_EQ(x86_64::Address::displace(x86_64::Address(reg, disp0), disp), + x86_64::Address(reg, disp0 + disp)); // Test SIB addressing with RBP base. - if (reg->AsRegister() != x86_64::RSP) { + if (reg.AsRegister() != x86_64::RSP) { for (ScaleFactor scale : scales) { - EXPECT_EQ(x86_64::Address::displace(x86_64::Address(*reg, scale, disp0), disp), - x86_64::Address(*reg, scale, disp0 + disp)); + EXPECT_EQ(x86_64::Address::displace(x86_64::Address(reg, scale, disp0), disp), + x86_64::Address(reg, scale, disp0 + disp)); } } // Test SIB addressing with different base. - for (const x86_64::CpuRegister* index : GetRegisters()) { - if (index->AsRegister() == x86_64::RSP) { + for (const x86_64::CpuRegister& index : GetRegisters()) { + if (index.AsRegister() == x86_64::RSP) { continue; // Skip RSP as it cannot be used with this address constructor. } for (ScaleFactor scale : scales) { - EXPECT_EQ(x86_64::Address::displace(x86_64::Address(*reg, *index, scale, disp0), disp), - x86_64::Address(*reg, *index, scale, disp0 + disp)); + EXPECT_EQ(x86_64::Address::displace(x86_64::Address(reg, index, scale, disp0), disp), + x86_64::Address(reg, index, scale, disp0 + disp)); } } |