riscv64: Add `enum AqRl` to assembler.

Make the acquire/release flags for atomic instructions more
verbose to avoid using wrong flags by mistake.

Also remove unnecessary members from x86 assembler tests
which should have been a part of the cleanup change
    https://android-review.googlesource.com/2697198 .

Test: m test-art-host-gtest
Bug: 283082089
Change-Id: I6a8e82d0019aae87f0d33cd1792caeb066182cf8

5 files changed, 97 insertions, 92 deletions

diff --git a/compiler/utils/riscv64/assembler_riscv64.cc b/compiler/utils/riscv64/assembler_riscv64.cc
index 00cc98a038..8662129604 100644
--- a/compiler/utils/riscv64/assembler_riscv64.cc
+++ b/compiler/utils/riscv64/assembler_riscv64.cc
@@ -389,92 +389,92 @@ void Riscv64Assembler::Remuw(XRegister rd, XRegister rs1, XRegister rs2) {
 
 /////////////////////////////// RV64 "A" Instructions  START ///////////////////////////////
 
-void Riscv64Assembler::LrW(XRegister rd, XRegister rs1, uint32_t aqrl) {
-  EmitR4(0x2, aqrl, 0x0, rs1, 0x2, rd, 0x2f);
+void Riscv64Assembler::LrW(XRegister rd, XRegister rs1, AqRl aqrl) {
+  EmitR4(0x2, enum_cast<uint32_t>(aqrl), 0x0, rs1, 0x2, rd, 0x2f);
 }
 
-void Riscv64Assembler::LrD(XRegister rd, XRegister rs1, uint32_t aqrl) {
-  EmitR4(0x2, aqrl, 0x0, rs1, 0x3, rd, 0x2f);
+void Riscv64Assembler::LrD(XRegister rd, XRegister rs1, AqRl aqrl) {
+  EmitR4(0x2, enum_cast<uint32_t>(aqrl), 0x0, rs1, 0x3, rd, 0x2f);
 }
 
-void Riscv64Assembler::ScW(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl) {
-  EmitR4(0x3, aqrl, rs2, rs1, 0x2, rd, 0x2f);
+void Riscv64Assembler::ScW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {
+  EmitR4(0x3, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f);
 }
 
-void Riscv64Assembler::ScD(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl) {
-  EmitR4(0x3, aqrl, rs2, rs1, 0x3, rd, 0x2f);
+void Riscv64Assembler::ScD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {
+  EmitR4(0x3, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f);
 }
 
-void Riscv64Assembler::AmoSwapW(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl) {
-  EmitR4(0x1, aqrl, rs2, rs1, 0x2, rd, 0x2f);
+void Riscv64Assembler::AmoSwapW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {
+  EmitR4(0x1, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f);
 }
 
-void Riscv64Assembler::AmoSwapD(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl) {
-  EmitR4(0x1, aqrl, rs2, rs1, 0x3, rd, 0x2f);
+void Riscv64Assembler::AmoSwapD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {
+  EmitR4(0x1, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f);
 }
 
-void Riscv64Assembler::AmoAddW(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl) {
-  EmitR4(0x0, aqrl, rs2, rs1, 0x2, rd, 0x2f);
+void Riscv64Assembler::AmoAddW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {
+  EmitR4(0x0, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f);
 }
 
-void Riscv64Assembler::AmoAddD(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl) {
-  EmitR4(0x0, aqrl, rs2, rs1, 0x3, rd, 0x2f);
+void Riscv64Assembler::AmoAddD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {
+  EmitR4(0x0, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f);
 }
 
-void Riscv64Assembler::AmoXorW(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl) {
-  EmitR4(0x4, aqrl, rs2, rs1, 0x2, rd, 0x2f);
+void Riscv64Assembler::AmoXorW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {
+  EmitR4(0x4, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f);
 }
 
-void Riscv64Assembler::AmoXorD(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl) {
-  EmitR4(0x4, aqrl, rs2, rs1, 0x3, rd, 0x2f);
+void Riscv64Assembler::AmoXorD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {
+  EmitR4(0x4, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f);
 }
 
-void Riscv64Assembler::AmoAndW(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl) {
-  EmitR4(0xc, aqrl, rs2, rs1, 0x2, rd, 0x2f);
+void Riscv64Assembler::AmoAndW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {
+  EmitR4(0xc, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f);
 }
 
-void Riscv64Assembler::AmoAndD(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl) {
-  EmitR4(0xc, aqrl, rs2, rs1, 0x3, rd, 0x2f);
+void Riscv64Assembler::AmoAndD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {
+  EmitR4(0xc, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f);
 }
 
-void Riscv64Assembler::AmoOrW(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl) {
-  EmitR4(0x8, aqrl, rs2, rs1, 0x2, rd, 0x2f);
+void Riscv64Assembler::AmoOrW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {
+  EmitR4(0x8, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f);
 }
 
-void Riscv64Assembler::AmoOrD(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl) {
-  EmitR4(0x8, aqrl, rs2, rs1, 0x3, rd, 0x2f);
+void Riscv64Assembler::AmoOrD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {
+  EmitR4(0x8, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f);
 }
 
-void Riscv64Assembler::AmoMinW(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl) {
-  EmitR4(0x10, aqrl, rs2, rs1, 0x2, rd, 0x2f);
+void Riscv64Assembler::AmoMinW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {
+  EmitR4(0x10, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f);
 }
 
-void Riscv64Assembler::AmoMinD(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl) {
-  EmitR4(0x10, aqrl, rs2, rs1, 0x3, rd, 0x2f);
+void Riscv64Assembler::AmoMinD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {
+  EmitR4(0x10, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f);
 }
 
-void Riscv64Assembler::AmoMaxW(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl) {
-  EmitR4(0x14, aqrl, rs2, rs1, 0x2, rd, 0x2f);
+void Riscv64Assembler::AmoMaxW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {
+  EmitR4(0x14, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f);
 }
 
-void Riscv64Assembler::AmoMaxD(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl) {
-  EmitR4(0x14, aqrl, rs2, rs1, 0x3, rd, 0x2f);
+void Riscv64Assembler::AmoMaxD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {
+  EmitR4(0x14, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f);
 }
 
-void Riscv64Assembler::AmoMinuW(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl) {
-  EmitR4(0x18, aqrl, rs2, rs1, 0x2, rd, 0x2f);
+void Riscv64Assembler::AmoMinuW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {
+  EmitR4(0x18, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f);
 }
 
-void Riscv64Assembler::AmoMinuD(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl) {
-  EmitR4(0x18, aqrl, rs2, rs1, 0x3, rd, 0x2f);
+void Riscv64Assembler::AmoMinuD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {
+  EmitR4(0x18, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f);
 }
 
-void Riscv64Assembler::AmoMaxuW(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl) {
-  EmitR4(0x1c, aqrl, rs2, rs1, 0x2, rd, 0x2f);
+void Riscv64Assembler::AmoMaxuW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {
+  EmitR4(0x1c, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x2, rd, 0x2f);
 }
 
-void Riscv64Assembler::AmoMaxuD(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl) {
-  EmitR4(0x1c, aqrl, rs2, rs1, 0x3, rd, 0x2f);
+void Riscv64Assembler::AmoMaxuD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl) {
+  EmitR4(0x1c, enum_cast<uint32_t>(aqrl), rs2, rs1, 0x3, rd, 0x2f);
 }
 
 /////////////////////////////// RV64 "A" Instructions  END ///////////////////////////////
diff --git a/compiler/utils/riscv64/assembler_riscv64.h b/compiler/utils/riscv64/assembler_riscv64.h
index 2ea751481a..6fe9e61b6b 100644
--- a/compiler/utils/riscv64/assembler_riscv64.h
+++ b/compiler/utils/riscv64/assembler_riscv64.h
@@ -36,6 +36,11 @@ namespace riscv64 {
 
 class ScratchRegisterScope;
 
+static constexpr size_t kRiscv64HalfwordSize = 2;
+static constexpr size_t kRiscv64WordSize = 4;
+static constexpr size_t kRiscv64DoublewordSize = 8;
+static constexpr size_t kRiscv64FloatRegSizeInBytes = 8;
+
 enum class FPRoundingMode : uint32_t {
   kRNE = 0x0,  // Round to Nearest, ties to Even
   kRTZ = 0x1,  // Round towards Zero
@@ -50,10 +55,12 @@ enum class FPRoundingMode : uint32_t {
   kIgnored = 0
 };
 
-static constexpr size_t kRiscv64HalfwordSize = 2;
-static constexpr size_t kRiscv64WordSize = 4;
-static constexpr size_t kRiscv64DoublewordSize = 8;
-static constexpr size_t kRiscv64FloatRegSizeInBytes = 8;
+enum class AqRl : uint32_t {
+  kNone    = 0x0,
+  kRelease = 0x1,
+  kAcquire = 0x2,
+  kAqRl    = kRelease | kAcquire
+};
 
 // the type for fence
 enum FenceType {
@@ -265,28 +272,28 @@ class Riscv64Assembler final : public Assembler {
   void Remuw(XRegister rd, XRegister rs1, XRegister rs2);
 
   // RV32A/RV64A Standard Extension
-  void LrW(XRegister rd, XRegister rs1, uint32_t aqrl);
-  void LrD(XRegister rd, XRegister rs1, uint32_t aqrl);
-  void ScW(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl);
-  void ScD(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl);
-  void AmoSwapW(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl);
-  void AmoSwapD(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl);
-  void AmoAddW(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl);
-  void AmoAddD(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl);
-  void AmoXorW(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl);
-  void AmoXorD(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl);
-  void AmoAndW(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl);
-  void AmoAndD(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl);
-  void AmoOrW(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl);
-  void AmoOrD(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl);
-  void AmoMinW(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl);
-  void AmoMinD(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl);
-  void AmoMaxW(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl);
-  void AmoMaxD(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl);
-  void AmoMinuW(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl);
-  void AmoMinuD(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl);
-  void AmoMaxuW(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl);
-  void AmoMaxuD(XRegister rd, XRegister rs2, XRegister rs1, uint32_t aqrl);
+  void LrW(XRegister rd, XRegister rs1, AqRl aqrl);
+  void LrD(XRegister rd, XRegister rs1, AqRl aqrl);
+  void ScW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl);
+  void ScD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl);
+  void AmoSwapW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl);
+  void AmoSwapD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl);
+  void AmoAddW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl);
+  void AmoAddD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl);
+  void AmoXorW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl);
+  void AmoXorD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl);
+  void AmoAndW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl);
+  void AmoAndD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl);
+  void AmoOrW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl);
+  void AmoOrD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl);
+  void AmoMinW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl);
+  void AmoMinD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl);
+  void AmoMaxW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl);
+  void AmoMaxD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl);
+  void AmoMinuW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl);
+  void AmoMinuD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl);
+  void AmoMaxuW(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl);
+  void AmoMaxuD(XRegister rd, XRegister rs2, XRegister rs1, AqRl aqrl);
 
   // "Zicsr" Standard Extension, opcode = 0x73, funct3 from 0x1 ~ 0x3 and 0x5 ~ 0x7
   void Csrrw(XRegister rd, uint32_t csr, XRegister rs1);
diff --git a/compiler/utils/riscv64/assembler_riscv64_test.cc b/compiler/utils/riscv64/assembler_riscv64_test.cc
index b3ead59d94..a345d6956c 100644
--- a/compiler/utils/riscv64/assembler_riscv64_test.cc
+++ b/compiler/utils/riscv64/assembler_riscv64_test.cc
@@ -970,20 +970,19 @@ class AssemblerRISCV64Test : public AssemblerTest<Riscv64Assembler,
                                                 fmt);
   }
 
-  std::string RepeatRRAqRl(void (Riscv64Assembler::*f)(XRegister, XRegister, uint32_t),
+  std::string RepeatRRAqRl(void (Riscv64Assembler::*f)(XRegister, XRegister, AqRl),
                            const std::string& fmt) {
     CHECK(f != nullptr);
-    std::vector<int64_t> imms = CreateImmediateValuesBits(2, /*as_uint=*/ true);
     std::string str;
     for (XRegister reg1 : GetRegisters()) {
       for (XRegister reg2 : GetRegisters()) {
-        for (int64_t imm : imms) {
-          (GetAssembler()->*f)(reg1, reg2, dchecked_integral_cast<uint32_t>(imm));
+        for (AqRl aqrl : kAqRls) {
+          (GetAssembler()->*f)(reg1, reg2, aqrl);
 
           std::string base = fmt;
           ReplaceReg(REG1_TOKEN, GetRegisterName(reg1), &base);
           ReplaceReg(REG2_TOKEN, GetRegisterName(reg2), &base);
-          ReplaceAqRl(imm, &base);
+          ReplaceAqRl(aqrl, &base);
           str += base;
           str += "\n";
         }
@@ -992,22 +991,21 @@ class AssemblerRISCV64Test : public AssemblerTest<Riscv64Assembler,
     return str;
   }
 
-  std::string RepeatRRRAqRl(void (Riscv64Assembler::*f)(XRegister, XRegister, XRegister, uint32_t),
+  std::string RepeatRRRAqRl(void (Riscv64Assembler::*f)(XRegister, XRegister, XRegister, AqRl),
                             const std::string& fmt) {
     CHECK(f != nullptr);
-    std::vector<int64_t> imms = CreateImmediateValuesBits(2, /*as_uint=*/ true);
     std::string str;
     for (XRegister reg1 : GetRegisters()) {
       for (XRegister reg2 : GetRegisters()) {
         for (XRegister reg3 : GetRegisters()) {
-          for (int64_t imm : imms) {
-            (GetAssembler()->*f)(reg1, reg2, reg3, dchecked_integral_cast<uint32_t>(imm));
+          for (AqRl aqrl : kAqRls) {
+            (GetAssembler()->*f)(reg1, reg2, reg3, aqrl);
 
             std::string base = fmt;
             ReplaceReg(REG1_TOKEN, GetRegisterName(reg1), &base);
             ReplaceReg(REG2_TOKEN, GetRegisterName(reg2), &base);
             ReplaceReg(REG3_TOKEN, GetRegisterName(reg3), &base);
-            ReplaceAqRl(imm, &base);
+            ReplaceAqRl(aqrl, &base);
             str += base;
             str += "\n";
           }
@@ -1110,6 +1108,8 @@ class AssemblerRISCV64Test : public AssemblerTest<Riscv64Assembler,
   static constexpr const char* CSR_TOKEN = "{csr}";
   static constexpr const char* UIMM_TOKEN = "{uimm}";
 
+  static constexpr AqRl kAqRls[] = { AqRl::kNone, AqRl::kRelease, AqRl::kAcquire, AqRl::kAqRl };
+
   static constexpr FPRoundingMode kRoundingModes[] = {
       FPRoundingMode::kRNE,
       FPRoundingMode::kRTZ,
@@ -1151,23 +1151,23 @@ class AssemblerRISCV64Test : public AssemblerTest<Riscv64Assembler,
     }
   }
 
-  void ReplaceAqRl(int64_t aqrl, /*inout*/ std::string* str) {
+  void ReplaceAqRl(AqRl aqrl, /*inout*/ std::string* str) {
     const char* replacement;
     switch (aqrl) {
-      case 0:
+      case AqRl::kNone:
         replacement = "";
         break;
-      case 1:
+      case AqRl::kRelease:
         replacement = ".rl";
         break;
-      case 2:
+      case AqRl::kAcquire:
         replacement = ".aq";
         break;
-      case 3:
+      case AqRl::kAqRl:
         replacement = ".aqrl";
         break;
       default:
-        LOG(FATAL) << "Unexpected value for `aqrl`: " << aqrl;
+        LOG(FATAL) << "Unexpected value for `aqrl`: " << enum_cast<uint32_t>(aqrl);
         UNREACHABLE();
     }
     size_t aqrl_index = str->find(AQRL_TOKEN);
diff --git a/compiler/utils/riscv64/jni_macro_assembler_riscv64.cc b/compiler/utils/riscv64/jni_macro_assembler_riscv64.cc
index 4a5c8099c9..3aeee8a154 100644
--- a/compiler/utils/riscv64/jni_macro_assembler_riscv64.cc
+++ b/compiler/utils/riscv64/jni_macro_assembler_riscv64.cc
@@ -458,12 +458,12 @@ void Riscv64JNIMacroAssembler::TryToTransitionFromRunnableToNative(
   Riscv64Label retry;
   __ Bind(&retry);
   static_assert(thread_flags_offset.Int32Value() == 0);  // LR/SC require exact address.
-  __ LrW(scratch, TR, /*aqrl=*/ 0u);
+  __ LrW(scratch, TR, AqRl::kNone);
   __ Li(scratch2, kNativeStateValue);
   // If any flags are set, go to the slow path.
   static_assert(kRunnableStateValue == 0u);
   __ Bnez(scratch, Riscv64JNIMacroLabel::Cast(label)->AsRiscv64());
-  __ ScW(scratch, scratch2, TR, /*aqrl=*/ 1u);  // Release.
+  __ ScW(scratch, scratch2, TR, AqRl::kRelease);
   __ Bnez(scratch, &retry);
 
   // Clear `self->tlsPtr_.held_mutexes[kMutatorLock]`.
@@ -492,14 +492,14 @@ void Riscv64JNIMacroAssembler::TryToTransitionFromNativeToRunnable(
   Riscv64Label retry;
   __ Bind(&retry);
   static_assert(thread_flags_offset.Int32Value() == 0);  // LR/SC require exact address.
-  __ LrW(scratch, TR, /*aqrl=*/ 2u);  // Acquire.
+  __ LrW(scratch, TR, AqRl::kAcquire);
   __ Li(scratch2, kNativeStateValue);
   // If any flags are set, or the state is not Native, go to the slow path.
   // (While the thread can theoretically transition between different Suspended states,
   // it would be very unexpected to see a state other than Native at this point.)
   __ Bne(scratch, scratch2, Riscv64JNIMacroLabel::Cast(label)->AsRiscv64());
   static_assert(kRunnableStateValue == 0u);
-  __ ScW(scratch, Zero, TR, /*aqrl=*/ 0u);
+  __ ScW(scratch, Zero, TR, AqRl::kNone);
   __ Bnez(scratch, &retry);
 
   // Set `self->tlsPtr_.held_mutexes[kMutatorLock]` to the mutator lock.
diff --git a/compiler/utils/x86/assembler_x86_test.cc b/compiler/utils/x86/assembler_x86_test.cc
index 36a67b0535..432322aea7 100644
--- a/compiler/utils/x86/assembler_x86_test.cc
+++ b/compiler/utils/x86/assembler_x86_test.cc
@@ -151,10 +151,8 @@ class AssemblerX86Test : public AssemblerTest<x86::X86Assembler,
 
  private:
   std::vector<x86::Address> addresses_;
-  std::vector<x86::Register> registers_;
   std::map<x86::Register, std::string, X86RegisterCompare> secondary_register_names_;
   std::map<x86::Register, std::string, X86RegisterCompare> tertiary_register_names_;
-  std::vector<x86::XmmRegister> fp_registers_;
 };
 
 class AssemblerX86AVXTest : public AssemblerX86Test {