diff options
| author | 2024-09-19 13:00:26 +0100 | |
|---|---|---|
| committer | 2024-09-19 13:47:52 +0000 | |
| commit | 44e2172427c83cb4974cd01c3fad61c6293fbb16 (patch) | |
| tree | 92d141cc5d0cfe35898cccee0958c9e01f8eff11 | |
| parent | 526a334716ee8a2967d83e0cac95cbc99cd7918f (diff) | |
Print the full relative address in Arm64
By printing with trailing zeroes (e.g. 0x00004074 instead of
0x4074) this brings Arm64 on par with other architectures.
Bug: 364443075
Fixes: 364443075
Test: art/test/testrunner/testrunner.py --target --64 --optimizing
Change-Id: Iade36a91316ca4310d71846ff2953ff7419877ee
| -rw-r--r-- | disassembler/disassembler_arm64.cc | 11 | ||||
| -rw-r--r-- | disassembler/disassembler_arm64.h | 4 | ||||
| -rw-r--r-- | test/1960-checker-bounds-codegen/src/Main.java | 6 |
3 files changed, 18 insertions, 3 deletions
diff --git a/disassembler/disassembler_arm64.cc b/disassembler/disassembler_arm64.cc index 23472a8dca..ef27e75c8c 100644 --- a/disassembler/disassembler_arm64.cc +++ b/disassembler/disassembler_arm64.cc @@ -60,6 +60,17 @@ void CustomDisassembler::AppendRegisterNameToOutput(const Instruction* instr, Disassembler::AppendRegisterNameToOutput(instr, reg); } +void CustomDisassembler::AppendCodeRelativeAddressToOutput(const Instruction* instr, + const void* addr) { + USE(instr); + int64_t rel_addr = CodeRelativeAddress(addr); + if (rel_addr >= 0) { + AppendToOutput("(addr 0x%08" PRIx64 ")", rel_addr); + } else { + AppendToOutput("(addr -0x%08" PRIx64 ")", -rel_addr); + } +} + void CustomDisassembler::Visit(vixl::aarch64::Metadata* metadata, const Instruction* instr) { vixl::aarch64::Disassembler::Visit(metadata, instr); const std::string& form = (*metadata)["form"]; diff --git a/disassembler/disassembler_arm64.h b/disassembler/disassembler_arm64.h index 7d49a03f58..d1b509127c 100644 --- a/disassembler/disassembler_arm64.h +++ b/disassembler/disassembler_arm64.h @@ -48,6 +48,10 @@ class CustomDisassembler final : public vixl::aarch64::Disassembler { void AppendRegisterNameToOutput(const vixl::aarch64::Instruction* instr, const vixl::aarch64::CPURegister& reg) override; + // Overriding to print the address with trailing zeroes e.g. 0x00004074 instead of 0x4074. + void AppendCodeRelativeAddressToOutput(const vixl::aarch64::Instruction* instr, + const void* addr) override; + // Intercepts the instruction flow captured by the parent method, // to specially instrument for particular instruction types. void Visit(vixl::aarch64::Metadata* metadata, const vixl::aarch64::Instruction* instr) override; diff --git a/test/1960-checker-bounds-codegen/src/Main.java b/test/1960-checker-bounds-codegen/src/Main.java index a84d67f694..40acee3477 100644 --- a/test/1960-checker-bounds-codegen/src/Main.java +++ b/test/1960-checker-bounds-codegen/src/Main.java @@ -24,7 +24,7 @@ public class Main { /// CHECK: cmp {{w\d+}}, #0x0 /// CHECK: b.ls #+0x{{[0-9a-f]+}} (addr 0x<<SLOW:[0-9a-f]+>>) /// CHECK: BoundsCheckSlowPathARM64 - /// CHECK-NEXT: 0x{{0*}}<<SLOW>>: + /// CHECK-NEXT: 0x<<SLOW>>: /// CHECK-START-ARM: int Main.constantIndex(int[]) disassembly (after) /// CHECK: BoundsCheck /// CHECK: cmp {{r\d+}}, #0 @@ -46,7 +46,7 @@ public class Main { /// CHECK: cmp {{w\d+}}, #0xa /// CHECK: b.hs #+0x{{[0-9a-f]+}} (addr 0x<<SLOW:[0-9a-f]+>>) /// CHECK: BoundsCheckSlowPathARM64 - /// CHECK-NEXT: 0x{{0*}}<<SLOW>>: + /// CHECK-NEXT: 0x<<SLOW>>: /// CHECK-START-ARM: int Main.constantLength(int) disassembly (after) /// CHECK: BoundsCheck /// CHECK: cmp {{r\d+}}, #10 @@ -70,7 +70,7 @@ public class Main { /// CHECK-NOT: cmp /// CHECK: b #+0x{{[0-9a-f]+}} (addr 0x<<SLOW:[0-9a-f]+>>) /// CHECK: BoundsCheckSlowPathARM64 - /// CHECK-NEXT: 0x{{0*}}<<SLOW>>: + /// CHECK-NEXT: 0x<<SLOW>>: /// CHECK-START-ARM: int Main.constantIndexAndLength() disassembly (after) /// CHECK: BoundsCheck /// CHECK-NOT: cmp |