Merge "Additional MIPS64 instructions needed by intrinsics code."

3 files changed, 280 insertions, 5 deletions

diff --git a/compiler/utils/mips64/assembler_mips64.cc b/compiler/utils/mips64/assembler_mips64.cc
index 24ea9e25db..b078f3e4cf 100644
--- a/compiler/utils/mips64/assembler_mips64.cc
+++ b/compiler/utils/mips64/assembler_mips64.cc
@@ -44,6 +44,32 @@ void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegis
   Emit(encoding);
 }
 
+void Mips64Assembler::EmitRsd(int opcode, GpuRegister rs, GpuRegister rd,
+                              int shamt, int funct) {
+  CHECK_NE(rs, kNoGpuRegister);
+  CHECK_NE(rd, kNoGpuRegister);
+  uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
+                      static_cast<uint32_t>(rs) << kRsShift |
+                      static_cast<uint32_t>(ZERO) << kRtShift |
+                      static_cast<uint32_t>(rd) << kRdShift |
+                      shamt << kShamtShift |
+                      funct;
+  Emit(encoding);
+}
+
+void Mips64Assembler::EmitRtd(int opcode, GpuRegister rt, GpuRegister rd,
+                              int shamt, int funct) {
+  CHECK_NE(rt, kNoGpuRegister);
+  CHECK_NE(rd, kNoGpuRegister);
+  uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
+                      static_cast<uint32_t>(ZERO) << kRsShift |
+                      static_cast<uint32_t>(rt) << kRtShift |
+                      static_cast<uint32_t>(rd) << kRdShift |
+                      shamt << kShamtShift |
+                      funct;
+  Emit(encoding);
+}
+
 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) {
   CHECK_NE(rs, kNoGpuRegister);
   CHECK_NE(rt, kNoGpuRegister);
@@ -235,6 +261,14 @@ void Mips64Assembler::Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
   EmitR(0, rs, rt, rd, 0, 0x27);
 }
 
+void Mips64Assembler::Bitswap(GpuRegister rd, GpuRegister rt) {
+  EmitRtd(0x1f, rt, rd, 0x0, 0x20);
+}
+
+void Mips64Assembler::Dbitswap(GpuRegister rd, GpuRegister rt) {
+  EmitRtd(0x1f, rt, rd, 0x0, 0x24);
+}
+
 void Mips64Assembler::Seb(GpuRegister rd, GpuRegister rt) {
   EmitR(0x1f, static_cast<GpuRegister>(0), rt, rd, 0x10, 0x20);
 }
@@ -243,12 +277,44 @@ void Mips64Assembler::Seh(GpuRegister rd, GpuRegister rt) {
   EmitR(0x1f, static_cast<GpuRegister>(0), rt, rd, 0x18, 0x20);
 }
 
+void Mips64Assembler::Dsbh(GpuRegister rd, GpuRegister rt) {
+  EmitRtd(0x1f, rt, rd, 0x2, 0x24);
+}
+
+void Mips64Assembler::Dshd(GpuRegister rd, GpuRegister rt) {
+  EmitRtd(0x1f, rt, rd, 0x5, 0x24);
+}
+
 void Mips64Assembler::Dext(GpuRegister rt, GpuRegister rs, int pos, int size_less_one) {
   DCHECK(0 <= pos && pos < 32) << pos;
   DCHECK(0 <= size_less_one && size_less_one < 32) << size_less_one;
   EmitR(0x1f, rs, rt, static_cast<GpuRegister>(size_less_one), pos, 3);
 }
 
+void Mips64Assembler::Wsbh(GpuRegister rd, GpuRegister rt) {
+  EmitRtd(0x1f, rt, rd, 2, 0x20);
+}
+
+void Mips64Assembler::Sc(GpuRegister rt, GpuRegister base, int16_t imm9) {
+  DCHECK((-256 <= imm9) && (imm9 < 256));
+  EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x26);
+}
+
+void Mips64Assembler::Scd(GpuRegister rt, GpuRegister base, int16_t imm9) {
+  DCHECK((-256 <= imm9) && (imm9 < 256));
+  EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x27);
+}
+
+void Mips64Assembler::Ll(GpuRegister rt, GpuRegister base, int16_t imm9) {
+  DCHECK((-256 <= imm9) && (imm9 < 256));
+  EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x36);
+}
+
+void Mips64Assembler::Lld(GpuRegister rt, GpuRegister base, int16_t imm9) {
+  DCHECK((-256 <= imm9) && (imm9 < 256));
+  EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x37);
+}
+
 void Mips64Assembler::Sll(GpuRegister rd, GpuRegister rt, int shamt) {
   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x00);
 }
@@ -257,6 +323,10 @@ void Mips64Assembler::Srl(GpuRegister rd, GpuRegister rt, int shamt) {
   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x02);
 }
 
+void Mips64Assembler::Rotr(GpuRegister rd, GpuRegister rt, int shamt) {
+  EmitR(0, static_cast<GpuRegister>(1), rt, rd, shamt, 0x02);
+}
+
 void Mips64Assembler::Sra(GpuRegister rd, GpuRegister rt, int shamt) {
   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x03);
 }
@@ -414,6 +484,30 @@ void Mips64Assembler::Jal(uint32_t addr26) {
   Nop();
 }
 
+void Mips64Assembler::Seleqz(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
+  EmitR(0, rs, rt, rd, 0, 0x35);
+}
+
+void Mips64Assembler::Selnez(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
+  EmitR(0, rs, rt, rd, 0, 0x37);
+}
+
+void Mips64Assembler::Clz(GpuRegister rd, GpuRegister rs) {
+  EmitRsd(0, rs, rd, 0x01, 0x10);
+}
+
+void Mips64Assembler::Clo(GpuRegister rd, GpuRegister rs) {
+  EmitRsd(0, rs, rd, 0x01, 0x11);
+}
+
+void Mips64Assembler::Dclz(GpuRegister rd, GpuRegister rs) {
+  EmitRsd(0, rs, rd, 0x01, 0x12);
+}
+
+void Mips64Assembler::Dclo(GpuRegister rd, GpuRegister rs) {
+  EmitRsd(0, rs, rd, 0x01, 0x13);
+}
+
 void Mips64Assembler::Jalr(GpuRegister rd, GpuRegister rs) {
   EmitR(0, rs, static_cast<GpuRegister>(0), rd, 0, 0x09);
   Nop();
@@ -543,6 +637,22 @@ void Mips64Assembler::DivD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
   EmitFR(0x11, 0x11, ft, fs, fd, 0x3);
 }
 
+void Mips64Assembler::SqrtS(FpuRegister fd, FpuRegister fs) {
+  EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x4);
+}
+
+void Mips64Assembler::SqrtD(FpuRegister fd, FpuRegister fs) {
+  EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x4);
+}
+
+void Mips64Assembler::AbsS(FpuRegister fd, FpuRegister fs) {
+  EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x5);
+}
+
+void Mips64Assembler::AbsD(FpuRegister fd, FpuRegister fs) {
+  EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x5);
+}
+
 void Mips64Assembler::MovS(FpuRegister fd, FpuRegister fs) {
   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x6);
 }
@@ -559,6 +669,94 @@ void Mips64Assembler::NegD(FpuRegister fd, FpuRegister fs) {
   EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x7);
 }
 
+void Mips64Assembler::RoundLS(FpuRegister fd, FpuRegister fs) {
+  EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x8);
+}
+
+void Mips64Assembler::RoundLD(FpuRegister fd, FpuRegister fs) {
+  EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x8);
+}
+
+void Mips64Assembler::RoundWS(FpuRegister fd, FpuRegister fs) {
+  EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xc);
+}
+
+void Mips64Assembler::RoundWD(FpuRegister fd, FpuRegister fs) {
+  EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xc);
+}
+
+void Mips64Assembler::CeilLS(FpuRegister fd, FpuRegister fs) {
+  EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xa);
+}
+
+void Mips64Assembler::CeilLD(FpuRegister fd, FpuRegister fs) {
+  EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xa);
+}
+
+void Mips64Assembler::CeilWS(FpuRegister fd, FpuRegister fs) {
+  EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xe);
+}
+
+void Mips64Assembler::CeilWD(FpuRegister fd, FpuRegister fs) {
+  EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xe);
+}
+
+void Mips64Assembler::FloorLS(FpuRegister fd, FpuRegister fs) {
+  EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xb);
+}
+
+void Mips64Assembler::FloorLD(FpuRegister fd, FpuRegister fs) {
+  EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xb);
+}
+
+void Mips64Assembler::FloorWS(FpuRegister fd, FpuRegister fs) {
+  EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xf);
+}
+
+void Mips64Assembler::FloorWD(FpuRegister fd, FpuRegister fs) {
+  EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xf);
+}
+
+void Mips64Assembler::SelS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
+  EmitFR(0x11, 0x10, ft, fs, fd, 0x10);
+}
+
+void Mips64Assembler::SelD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
+  EmitFR(0x11, 0x11, ft, fs, fd, 0x10);
+}
+
+void Mips64Assembler::RintS(FpuRegister fd, FpuRegister fs) {
+  EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x1a);
+}
+
+void Mips64Assembler::RintD(FpuRegister fd, FpuRegister fs) {
+  EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x1a);
+}
+
+void Mips64Assembler::ClassS(FpuRegister fd, FpuRegister fs) {
+  EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x1b);
+}
+
+void Mips64Assembler::ClassD(FpuRegister fd, FpuRegister fs) {
+  EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x1b);
+}
+
+void Mips64Assembler::MinS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
+  EmitFR(0x11, 0x10, ft, fs, fd, 0x1c);
+}
+
+void Mips64Assembler::MinD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
+  EmitFR(0x11, 0x11, ft, fs, fd, 0x1c);
+}
+
+void Mips64Assembler::MaxS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
+  EmitFR(0x11, 0x10, ft, fs, fd, 0x1e);
+}
+
+void Mips64Assembler::MaxD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
+  EmitFR(0x11, 0x11, ft, fs, fd, 0x1e);
+}
+
 void Mips64Assembler::Cvtsw(FpuRegister fd, FpuRegister fs) {
   EmitFR(0x11, 0x14, static_cast<FpuRegister>(0), fs, fd, 0x20);
 }
@@ -575,6 +773,10 @@ void Mips64Assembler::Cvtds(FpuRegister fd, FpuRegister fs) {
   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x21);
 }
 
+void Mips64Assembler::Cvtdl(FpuRegister fd, FpuRegister fs) {
+  EmitFR(0x11, 0x15, static_cast<FpuRegister>(0), fs, fd, 0x21);
+}
+
 void Mips64Assembler::Mfc1(GpuRegister rt, FpuRegister fs) {
   EmitFR(0x11, 0x00, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
 }
diff --git a/compiler/utils/mips64/assembler_mips64.h b/compiler/utils/mips64/assembler_mips64.h
index 31130ea43d..a120abb238 100644
--- a/compiler/utils/mips64/assembler_mips64.h
+++ b/compiler/utils/mips64/assembler_mips64.h
@@ -90,12 +90,22 @@ class Mips64Assembler FINAL : public Assembler {
   void Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16);
   void Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt);
 
+  void Bitswap(GpuRegister rd, GpuRegister rt);  // R6
+  void Dbitswap(GpuRegister rd, GpuRegister rt);  // R6
   void Seb(GpuRegister rd, GpuRegister rt);  // R2+
   void Seh(GpuRegister rd, GpuRegister rt);  // R2+
+  void Dsbh(GpuRegister rd, GpuRegister rt);  // R2+
+  void Dshd(GpuRegister rd, GpuRegister rt);  // R2+
   void Dext(GpuRegister rs, GpuRegister rt, int pos, int size_less_one);  // MIPS64
+  void Wsbh(GpuRegister rd, GpuRegister rt);
+  void Sc(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);
+  void Scd(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);
+  void Ll(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);
+  void Lld(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);
 
   void Sll(GpuRegister rd, GpuRegister rt, int shamt);
   void Srl(GpuRegister rd, GpuRegister rt, int shamt);
+  void Rotr(GpuRegister rd, GpuRegister rt, int shamt);
   void Sra(GpuRegister rd, GpuRegister rt, int shamt);
   void Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs);
   void Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs);
@@ -133,6 +143,12 @@ class Mips64Assembler FINAL : public Assembler {
   void Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
   void Slti(GpuRegister rt, GpuRegister rs, uint16_t imm16);
   void Sltiu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
+  void Seleqz(GpuRegister rd, GpuRegister rs, GpuRegister rt);
+  void Selnez(GpuRegister rd, GpuRegister rs, GpuRegister rt);
+  void Clz(GpuRegister rd, GpuRegister rs);
+  void Clo(GpuRegister rd, GpuRegister rs);
+  void Dclz(GpuRegister rd, GpuRegister rs);
+  void Dclo(GpuRegister rd, GpuRegister rs);
 
   void Beq(GpuRegister rs, GpuRegister rt, uint16_t imm16);
   void Bne(GpuRegister rs, GpuRegister rt, uint16_t imm16);
@@ -165,15 +181,42 @@ class Mips64Assembler FINAL : public Assembler {
   void SubD(FpuRegister fd, FpuRegister fs, FpuRegister ft);
   void MulD(FpuRegister fd, FpuRegister fs, FpuRegister ft);
   void DivD(FpuRegister fd, FpuRegister fs, FpuRegister ft);
+  void SqrtS(FpuRegister fd, FpuRegister fs);
+  void SqrtD(FpuRegister fd, FpuRegister fs);
+  void AbsS(FpuRegister fd, FpuRegister fs);
+  void AbsD(FpuRegister fd, FpuRegister fs);
   void MovS(FpuRegister fd, FpuRegister fs);
   void MovD(FpuRegister fd, FpuRegister fs);
   void NegS(FpuRegister fd, FpuRegister fs);
   void NegD(FpuRegister fd, FpuRegister fs);
+  void RoundLS(FpuRegister fd, FpuRegister fs);
+  void RoundLD(FpuRegister fd, FpuRegister fs);
+  void RoundWS(FpuRegister fd, FpuRegister fs);
+  void RoundWD(FpuRegister fd, FpuRegister fs);
+  void CeilLS(FpuRegister fd, FpuRegister fs);
+  void CeilLD(FpuRegister fd, FpuRegister fs);
+  void CeilWS(FpuRegister fd, FpuRegister fs);
+  void CeilWD(FpuRegister fd, FpuRegister fs);
+  void FloorLS(FpuRegister fd, FpuRegister fs);
+  void FloorLD(FpuRegister fd, FpuRegister fs);
+  void FloorWS(FpuRegister fd, FpuRegister fs);
+  void FloorWD(FpuRegister fd, FpuRegister fs);
+  void SelS(FpuRegister fd, FpuRegister fs, FpuRegister ft);
+  void SelD(FpuRegister fd, FpuRegister fs, FpuRegister ft);
+  void RintS(FpuRegister fd, FpuRegister fs);
+  void RintD(FpuRegister fd, FpuRegister fs);
+  void ClassS(FpuRegister fd, FpuRegister fs);
+  void ClassD(FpuRegister fd, FpuRegister fs);
+  void MinS(FpuRegister fd, FpuRegister fs, FpuRegister ft);
+  void MinD(FpuRegister fd, FpuRegister fs, FpuRegister ft);
+  void MaxS(FpuRegister fd, FpuRegister fs, FpuRegister ft);
+  void MaxD(FpuRegister fd, FpuRegister fs, FpuRegister ft);
 
   void Cvtsw(FpuRegister fd, FpuRegister fs);
   void Cvtdw(FpuRegister fd, FpuRegister fs);
   void Cvtsd(FpuRegister fd, FpuRegister fs);
   void Cvtds(FpuRegister fd, FpuRegister fs);
+  void Cvtdl(FpuRegister fd, FpuRegister fs);
 
   void Mfc1(GpuRegister rt, FpuRegister fs);
   void Mtc1(GpuRegister rt, FpuRegister fs);
@@ -342,6 +385,8 @@ class Mips64Assembler FINAL : public Assembler {
 
  private:
   void EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, int shamt, int funct);
+  void EmitRsd(int opcode, GpuRegister rs, GpuRegister rd, int shamt, int funct);
+  void EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, int shamt, int funct);
   void EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm);
   void EmitI21(int opcode, GpuRegister rs, uint32_t imm21);
   void EmitJ(int opcode, uint32_t addr26);
diff --git a/disassembler/disassembler_mips.cc b/disassembler/disassembler_mips.cc
index 70ca88dc55..c55d285f9f 100644
--- a/disassembler/disassembler_mips.cc
+++ b/disassembler/disassembler_mips.cc
@@ -46,6 +46,7 @@ static const uint32_t kJTypeMask = (0x3f << kOpcodeShift);
 static const uint32_t kRTypeMask = ((0x3f << kOpcodeShift) | (0x3f));
 static const uint32_t kSpecial0Mask = (0x3f << kOpcodeShift);
 static const uint32_t kSpecial2Mask = (0x3f << kOpcodeShift);
+static const uint32_t kSpecial3Mask = (0x3f << kOpcodeShift);
 static const uint32_t kFpMask = kRTypeMask;
 
 static const MipsInstruction gMipsInstructions[] = {
@@ -98,7 +99,6 @@ static const MipsInstruction gMipsInstructions[] = {
   { kRTypeMask, 46, "dsub", "DST", },
   { kRTypeMask, 47, "dsubu", "DST", },
   // TODO: tge[u], tlt[u], teg, tne
-  // TODO: seleqz, selnez
   { kRTypeMask, 56, "dsll", "DTA", },
   { kRTypeMask, 58, "dsrl", "DTA", },
   { kRTypeMask, 59, "dsra", "DTA", },
@@ -106,9 +106,6 @@ static const MipsInstruction gMipsInstructions[] = {
   { kRTypeMask | (0x1f << 21), 62 | (1 << 21), "drotr32", "DTA", },
   { kRTypeMask, 62, "dsrl32", "DTA", },
   { kRTypeMask, 63, "dsra32", "DTA", },
-  { kRTypeMask, (31u << kOpcodeShift) | 3, "dext", "TSAZ", },
-  { kRTypeMask | (0x1f << 21) | (0x1f << 6), (31u << 26) | (16 << 6) | 32, "seb", "DT", },
-  { kRTypeMask | (0x1f << 21) | (0x1f << 6), (31u << 26) | (24 << 6) | 32, "seh", "DT", },
 
   // SPECIAL0
   { kSpecial0Mask | 0x7ff, (2 << 6) | 24, "mul", "DST" },
@@ -127,7 +124,13 @@ static const MipsInstruction gMipsInstructions[] = {
   { kSpecial0Mask | 0x7ff, (3 << 6) | 30, "dmod", "DST" },
   { kSpecial0Mask | 0x7ff, (2 << 6) | 31, "ddivu", "DST" },
   { kSpecial0Mask | 0x7ff, (3 << 6) | 31, "dmodu", "DST" },
-  // TODO: [d]clz, [d]clo
+  { kSpecial0Mask | 0x7ff, (0 << 6) | 53, "seleqz", "DST" },
+  { kSpecial0Mask | 0x7ff, (0 << 6) | 55, "selnez", "DST" },
+  { kSpecial0Mask | (0x1f << 21) | 0x3f, (1 << 21) | 2, "rotr", "DTA", },
+  { kSpecial0Mask | (0x1f << 16) | 0x7ff, (0x01 << 6) | 0x10, "clz", "DS" },
+  { kSpecial0Mask | (0x1f << 16) | 0x7ff, (0x01 << 6) | 0x11, "clo", "DS" },
+  { kSpecial0Mask | (0x1f << 16) | 0x7ff, (0x01 << 6) | 0x12, "dclz", "DS" },
+  { kSpecial0Mask | (0x1f << 16) | 0x7ff, (0x01 << 6) | 0x13, "dclo", "DS" },
   // TODO: sdbbp
 
   // SPECIAL2
@@ -140,6 +143,20 @@ static const MipsInstruction gMipsInstructions[] = {
   { kSpecial2Mask | 0xffff, (28 << kOpcodeShift) | 5, "msubu", "ST" },
   { kSpecial2Mask | 0x3f, (28 << kOpcodeShift) | 0x3f, "sdbbp", "" },  // TODO: code
 
+  // SPECIAL3
+  { kSpecial3Mask | 0x3f, (31 << kOpcodeShift) | 3, "dext", "TSAZ", },
+  { kSpecial3Mask | (0x1f << 21) | (0x1f << 6) | 0x3f, (31 << kOpcodeShift) | (16 << 6) | 32, "seb", "DT", },
+  { kSpecial3Mask | (0x1f << 21) | (0x1f << 6) | 0x3f, (31 << kOpcodeShift) | (24 << 6) | 32, "seh", "DT", },
+  { kSpecial3Mask | (0x1f << 21) | (0x1f << 6) | 0x3f, (31 << kOpcodeShift) | 32, "bitswap", "DT", },
+  { kSpecial3Mask | (0x1f << 21) | (0x1f << 6) | 0x3f, (31 << kOpcodeShift) | 36, "dbitswap", "DT", },
+  { kSpecial3Mask | (0x1f << 21) | (0x1f << 6) | 0x3f, (31 << kOpcodeShift) | (2 << 6) | 36, "dsbh", "DT", },
+  { kSpecial3Mask | (0x1f << 21) | (0x1f << 6) | 0x3f, (31 << kOpcodeShift) | (5 << 6) | 36, "dshd", "DT", },
+  { kSpecial3Mask | (0x1f << 21) | (0x1f << 6) | 0x3f, (31 << kOpcodeShift) | (2 << 6) | 32, "wsbh", "DT", },
+  { kSpecial3Mask | 0x7f, (31 << kOpcodeShift) | 0x26, "sc", "Tl", },
+  { kSpecial3Mask | 0x7f, (31 << kOpcodeShift) | 0x27, "scd", "Tl", },
+  { kSpecial3Mask | 0x7f, (31 << kOpcodeShift) | 0x36, "ll", "Tl", },
+  { kSpecial3Mask | 0x7f, (31 << kOpcodeShift) | 0x37, "lld", "Tl", },
+
   // J-type instructions.
   { kJTypeMask, 2 << kOpcodeShift, "j", "L" },
   { kJTypeMask, 3 << kOpcodeShift, "jal", "L" },
@@ -305,11 +322,16 @@ static const MipsInstruction gMipsInstructions[] = {
   { kFpMask | (0x21f << 16), kCop1 | (0x200 << 16) | 13, "trunc.w", "fad" },
   { kFpMask | (0x21f << 16), kCop1 | (0x200 << 16) | 14, "ceil.w", "fad" },
   { kFpMask | (0x21f << 16), kCop1 | (0x200 << 16) | 15, "floor.w", "fad" },
+  { kFpMask | (0x21f << 16), kCop1 | (0x200 << 16) | 26, "rint", "fad" },
+  { kFpMask | (0x21f << 16), kCop1 | (0x200 << 16) | 27, "class", "fad" },
   { kFpMask | (0x21f << 16), kCop1 | (0x200 << 16) | 32, "cvt.s", "fad" },
   { kFpMask | (0x21f << 16), kCop1 | (0x200 << 16) | 33, "cvt.d", "fad" },
   { kFpMask | (0x21f << 16), kCop1 | (0x200 << 16) | 36, "cvt.w", "fad" },
   { kFpMask | (0x21f << 16), kCop1 | (0x200 << 16) | 37, "cvt.l", "fad" },
   { kFpMask | (0x21f << 16), kCop1 | (0x200 << 16) | 38, "cvt.ps", "fad" },
+  { kFpMask, kCop1 | 0x10, "sel", "fadt" },
+  { kFpMask, kCop1 | 0x1e, "max", "fadt" },
+  { kFpMask, kCop1 | 0x1c, "min", "fadt" },
 };
 
 static uint32_t ReadU32(const uint8_t* ptr) {
@@ -390,6 +412,12 @@ size_t DisassemblerMips::Dump(std::ostream& os, const uint8_t* instr_ptr) {
               args << reinterpret_cast<void*>(target);
             }
             break;
+          case 'l':  // 9-bit signed offset
+            {
+              int32_t offset = static_cast<int16_t>(instruction) >> 7;
+              args << StringPrintf("%+d(r%d)", offset, rs);
+            }
+            break;
           case 'O':  // +x(rs)
             {
               int32_t offset = static_cast<int16_t>(instruction & 0xffff);