[Compiler] Add object ref discovery

Previously, the compiler ran a type inference pass to identify floating
point uses for register allocation.  The grand plan involves moving
all type inference into the Art compiler driver (using the results from
verification).  As a short-term workaround, this CL adds object reference
discovery to the type inference pass.  This is needed for LLVM-IR generation.

Change-Id: I655806264181bfd26ab9340582a02c657cd3f678

10 files changed, 289 insertions, 251 deletions

diff --git a/src/compiler/CompilerIR.h b/src/compiler/CompilerIR.h
index 2e0f6d5bae..972bfac4be 100644
--- a/src/compiler/CompilerIR.h
+++ b/src/compiler/CompilerIR.h
@@ -64,6 +64,7 @@ struct RegLocation {
   unsigned defined:1;   // Do we know the type?
   unsigned fp:1;        // Floating point?
   unsigned core:1;      // Non-floating point?
+  unsigned ref:1;       // Something GC cares about
   unsigned highWord:1;  // High word of pair?
   unsigned home:1;      // Does this represent the home location?
   u1 lowReg;            // First physical register
diff --git a/src/compiler/Dataflow.cc b/src/compiler/Dataflow.cc
index 2ba0cc1f96..3d2ac5d3de 100644
--- a/src/compiler/Dataflow.cc
+++ b/src/compiler/Dataflow.cc
@@ -42,31 +42,31 @@ const int oatDataFlowAttributes[kMirOpLast] = {
   DF_DA | DF_UB | DF_IS_MOVE,
 
   // 04 MOVE_WIDE vA, vB
-  DF_DA_WIDE | DF_UB_WIDE | DF_IS_MOVE,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
 
   // 05 MOVE_WIDE_FROM16 vAA, vBBBB
-  DF_DA_WIDE | DF_UB_WIDE | DF_IS_MOVE,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
 
   // 06 MOVE_WIDE_16 vAAAA, vBBBB
-  DF_DA_WIDE | DF_UB_WIDE | DF_IS_MOVE,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
 
   // 07 MOVE_OBJECT vA, vB
-  DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_CORE_A | DF_CORE_B,
+  DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_REF_A | DF_REF_B,
 
   // 08 MOVE_OBJECT_FROM16 vAA, vBBBB
-  DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_CORE_A | DF_CORE_B,
+  DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_REF_A | DF_REF_B,
 
   // 09 MOVE_OBJECT_16 vAAAA, vBBBB
-  DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_CORE_A | DF_CORE_B,
+  DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_REF_A | DF_REF_B,
 
   // 0A MOVE_RESULT vAA
   DF_DA,
 
   // 0B MOVE_RESULT_WIDE vAA
-  DF_DA_WIDE,
+  DF_DA | DF_A_WIDE,
 
   // 0C MOVE_RESULT_OBJECT vAA
-  DF_DA | DF_CORE_A,
+  DF_DA | DF_REF_A,
 
   // 0D MOVE_EXCEPTION vAA
   DF_DA | DF_CORE_A,
@@ -78,10 +78,10 @@ const int oatDataFlowAttributes[kMirOpLast] = {
   DF_UA,
 
   // 10 RETURN_WIDE vAA
-  DF_UA_WIDE,
+  DF_UA | DF_A_WIDE,
 
   // 11 RETURN_OBJECT vAA
-  DF_UA | DF_CORE_A,
+  DF_UA | DF_REF_A,
 
   // 12 CONST_4 vA, #+B
   DF_DA | DF_SETS_CONST,
@@ -96,46 +96,46 @@ const int oatDataFlowAttributes[kMirOpLast] = {
   DF_DA | DF_SETS_CONST,
 
   // 16 CONST_WIDE_16 vAA, #+BBBB
-  DF_DA_WIDE | DF_SETS_CONST,
+  DF_DA | DF_A_WIDE | DF_SETS_CONST,
 
   // 17 CONST_WIDE_32 vAA, #+BBBBBBBB
-  DF_DA_WIDE | DF_SETS_CONST,
+  DF_DA | DF_A_WIDE | DF_SETS_CONST,
 
   // 18 CONST_WIDE vAA, #+BBBBBBBBBBBBBBBB
-  DF_DA_WIDE | DF_SETS_CONST,
+  DF_DA | DF_A_WIDE | DF_SETS_CONST,
 
   // 19 CONST_WIDE_HIGH16 vAA, #+BBBB000000000000
-  DF_DA_WIDE | DF_SETS_CONST,
+  DF_DA | DF_A_WIDE | DF_SETS_CONST,
 
   // 1A CONST_STRING vAA, string@BBBB
-  DF_DA | DF_CORE_A,
+  DF_DA | DF_REF_A,
 
   // 1B CONST_STRING_JUMBO vAA, string@BBBBBBBB
-  DF_DA | DF_CORE_A,
+  DF_DA | DF_REF_A,
 
   // 1C CONST_CLASS vAA, type@BBBB
-  DF_DA | DF_CORE_A,
+  DF_DA | DF_REF_A,
 
   // 1D MONITOR_ENTER vAA
-  DF_UA | DF_NULL_CHK_0 | DF_CORE_A,
+  DF_UA | DF_NULL_CHK_0 | DF_REF_A,
 
   // 1E MONITOR_EXIT vAA
-  DF_UA | DF_NULL_CHK_0 | DF_CORE_A,
+  DF_UA | DF_NULL_CHK_0 | DF_REF_A,
 
   // 1F CHK_CAST vAA, type@BBBB
-  DF_UA | DF_CORE_A | DF_UMS,
+  DF_UA | DF_REF_A | DF_UMS,
 
   // 20 INSTANCE_OF vA, vB, type@CCCC
-  DF_DA | DF_UB | DF_CORE_A | DF_CORE_B | DF_UMS,
+  DF_DA | DF_UB | DF_CORE_A | DF_REF_B | DF_UMS,
 
   // 21 ARRAY_LENGTH vA, vB
-  DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_A | DF_CORE_B,
+  DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_A | DF_REF_B,
 
   // 22 NEW_INSTANCE vAA, type@BBBB
-  DF_DA | DF_NON_NULL_DST | DF_CORE_A | DF_UMS,
+  DF_DA | DF_NON_NULL_DST | DF_REF_A | DF_UMS,
 
   // 23 NEW_ARRAY vA, vB, type@CCCC
-  DF_DA | DF_UB | DF_NON_NULL_DST | DF_CORE_A | DF_CORE_B | DF_UMS,
+  DF_DA | DF_UB | DF_NON_NULL_DST | DF_REF_A | DF_CORE_B | DF_UMS,
 
   // 24 FILLED_NEW_ARRAY {vD, vE, vF, vG, vA}
   DF_FORMAT_35C | DF_NON_NULL_RET | DF_UMS,
@@ -144,10 +144,10 @@ const int oatDataFlowAttributes[kMirOpLast] = {
   DF_FORMAT_3RC | DF_NON_NULL_RET | DF_UMS,
 
   // 26 FILL_ARRAY_DATA vAA, +BBBBBBBB
-  DF_UA | DF_CORE_A | DF_UMS,
+  DF_UA | DF_REF_A | DF_UMS,
 
   // 27 THROW vAA
-  DF_UA | DF_CORE_A | DF_UMS,
+  DF_UA | DF_REF_A | DF_UMS,
 
   // 28 GOTO
   DF_NOP,
@@ -171,13 +171,13 @@ const int oatDataFlowAttributes[kMirOpLast] = {
   DF_DA | DF_UB | DF_UC | DF_FP_B | DF_FP_C | DF_CORE_A,
 
   // 2F CMPL_DOUBLE vAA, vBB, vCC
-  DF_DA | DF_UB_WIDE | DF_UC_WIDE | DF_FP_B | DF_FP_C | DF_CORE_A,
+  DF_DA | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_B | DF_FP_C | DF_CORE_A,
 
   // 30 CMPG_DOUBLE vAA, vBB, vCC
-  DF_DA | DF_UB_WIDE | DF_UC_WIDE | DF_FP_B | DF_FP_C | DF_CORE_A,
+  DF_DA | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_B | DF_FP_C | DF_CORE_A,
 
   // 31 CMP_LONG vAA, vBB, vCC
-  DF_DA | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
+  DF_DA | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
   // 32 IF_EQ vA, vB, +CCCC
   DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
@@ -235,97 +235,97 @@ const int oatDataFlowAttributes[kMirOpLast] = {
   DF_NOP,
 
   // 44 AGET vAA, vBB, vCC
-  DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_CORE_B | DF_CORE_C,
+  DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C,
 
   // 45 AGET_WIDE vAA, vBB, vCC
-  DF_DA_WIDE | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_CORE_B | DF_CORE_C,
+  DF_DA | DF_A_WIDE | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C,
 
   // 46 AGET_OBJECT vAA, vBB, vCC
-  DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_CORE_B | DF_CORE_C,
+  DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_A | DF_REF_B | DF_CORE_C,
 
   // 47 AGET_BOOLEAN vAA, vBB, vCC
-  DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_CORE_B | DF_CORE_C,
+  DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C,
 
   // 48 AGET_BYTE vAA, vBB, vCC
-  DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_CORE_B | DF_CORE_C,
+  DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C,
 
   // 49 AGET_CHAR vAA, vBB, vCC
-  DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_CORE_B | DF_CORE_C,
+  DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C,
 
   // 4A AGET_SHORT vAA, vBB, vCC
-  DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_CORE_B | DF_CORE_C,
+  DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C,
 
   // 4B APUT vAA, vBB, vCC
-  DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_CORE_B | DF_CORE_C,
+  DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_B | DF_CORE_C,
 
   // 4C APUT_WIDE vAA, vBB, vCC
-  DF_UA_WIDE | DF_UB | DF_UC | DF_NULL_CHK_2 | DF_RANGE_CHK_3 | DF_CORE_B | DF_CORE_C,
+  DF_UA | DF_A_WIDE | DF_UB | DF_UC | DF_NULL_CHK_2 | DF_RANGE_CHK_3 | DF_REF_B | DF_CORE_C,
 
   // 4D APUT_OBJECT vAA, vBB, vCC
-  DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_CORE_B | DF_CORE_C,
+  DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_A | DF_REF_B | DF_CORE_C,
 
   // 4E APUT_BOOLEAN vAA, vBB, vCC
-  DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_CORE_B | DF_CORE_C,
+  DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_B | DF_CORE_C,
 
   // 4F APUT_BYTE vAA, vBB, vCC
-  DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_CORE_B | DF_CORE_C,
+  DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_B | DF_CORE_C,
 
   // 50 APUT_CHAR vAA, vBB, vCC
-  DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_CORE_B | DF_CORE_C,
+  DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_B | DF_CORE_C,
 
   // 51 APUT_SHORT vAA, vBB, vCC
-  DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_CORE_B | DF_CORE_C,
+  DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_B | DF_CORE_C,
 
   // 52 IGET vA, vB, field@CCCC
-  DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_B,
+  DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
 
   // 53 IGET_WIDE vA, vB, field@CCCC
-  DF_DA_WIDE | DF_UB | DF_NULL_CHK_0 | DF_CORE_B,
+  DF_DA | DF_A_WIDE | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
 
   // 54 IGET_OBJECT vA, vB, field@CCCC
-  DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_B,
+  DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_A | DF_REF_B,
 
   // 55 IGET_BOOLEAN vA, vB, field@CCCC
-  DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_B,
+  DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
 
   // 56 IGET_BYTE vA, vB, field@CCCC
-  DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_B,
+  DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
 
   // 57 IGET_CHAR vA, vB, field@CCCC
-  DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_B,
+  DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
 
   // 58 IGET_SHORT vA, vB, field@CCCC
-  DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_B,
+  DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
 
   // 59 IPUT vA, vB, field@CCCC
-  DF_UA | DF_UB | DF_NULL_CHK_1 | DF_CORE_B,
+  DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B,
 
   // 5A IPUT_WIDE vA, vB, field@CCCC
-  DF_UA_WIDE | DF_UB | DF_NULL_CHK_2 | DF_CORE_B,
+  DF_UA | DF_A_WIDE | DF_UB | DF_NULL_CHK_2 | DF_REF_B,
 
   // 5B IPUT_OBJECT vA, vB, field@CCCC
-  DF_UA | DF_UB | DF_NULL_CHK_1 | DF_CORE_B,
+  DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_A | DF_REF_B,
 
   // 5C IPUT_BOOLEAN vA, vB, field@CCCC
-  DF_UA | DF_UB | DF_NULL_CHK_1 | DF_CORE_B,
+  DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B,
 
   // 5D IPUT_BYTE vA, vB, field@CCCC
-  DF_UA | DF_UB | DF_NULL_CHK_1 | DF_CORE_B,
+  DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B,
 
   // 5E IPUT_CHAR vA, vB, field@CCCC
-  DF_UA | DF_UB | DF_NULL_CHK_1 | DF_CORE_B,
+  DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B,
 
   // 5F IPUT_SHORT vA, vB, field@CCCC
-  DF_UA | DF_UB | DF_NULL_CHK_1 | DF_CORE_B,
+  DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B,
 
   // 60 SGET vAA, field@BBBB
   DF_DA | DF_UMS,
 
   // 61 SGET_WIDE vAA, field@BBBB
-  DF_DA_WIDE | DF_UMS,
+  DF_DA | DF_A_WIDE | DF_UMS,
 
   // 62 SGET_OBJECT vAA, field@BBBB
-  DF_DA | DF_CORE_A | DF_UMS,
+  DF_DA | DF_REF_A | DF_UMS,
 
   // 63 SGET_BOOLEAN vAA, field@BBBB
   DF_DA | DF_UMS,
@@ -343,10 +343,10 @@ const int oatDataFlowAttributes[kMirOpLast] = {
   DF_UA | DF_UMS,
 
   // 68 SPUT_WIDE vAA, field@BBBB
-  DF_UA_WIDE | DF_UMS,
+  DF_UA | DF_A_WIDE | DF_UMS,
 
   // 69 SPUT_OBJECT vAA, field@BBBB
-  DF_UA | DF_CORE_A | DF_UMS,
+  DF_UA | DF_REF_A | DF_UMS,
 
   // 6A SPUT_BOOLEAN vAA, field@BBBB
   DF_UA | DF_UMS,
@@ -406,52 +406,52 @@ const int oatDataFlowAttributes[kMirOpLast] = {
   DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
   // 7D NEG_LONG vA, vB
-  DF_DA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
 
   // 7E NOT_LONG vA, vB
-  DF_DA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
 
   // 7F NEG_FLOAT vA, vB
   DF_DA | DF_UB | DF_FP_A | DF_FP_B,
 
   // 80 NEG_DOUBLE vA, vB
-  DF_DA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
 
   // 81 INT_TO_LONG vA, vB
-  DF_DA_WIDE | DF_UB | DF_CORE_A | DF_CORE_B,
+  DF_DA | DF_A_WIDE | DF_UB | DF_CORE_A | DF_CORE_B,
 
   // 82 INT_TO_FLOAT vA, vB
   DF_DA | DF_UB | DF_FP_A | DF_CORE_B,
 
   // 83 INT_TO_DOUBLE vA, vB
-  DF_DA_WIDE | DF_UB | DF_FP_A | DF_CORE_B,
+  DF_DA | DF_A_WIDE | DF_UB | DF_FP_A | DF_CORE_B,
 
   // 84 LONG_TO_INT vA, vB
-  DF_DA | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
+  DF_DA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
 
   // 85 LONG_TO_FLOAT vA, vB
-  DF_DA | DF_UB_WIDE | DF_FP_A | DF_CORE_B,
+  DF_DA | DF_UB | DF_B_WIDE | DF_FP_A | DF_CORE_B,
 
   // 86 LONG_TO_DOUBLE vA, vB
-  DF_DA_WIDE | DF_UB_WIDE | DF_FP_A | DF_CORE_B,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_A | DF_CORE_B,
 
   // 87 FLOAT_TO_INT vA, vB
   DF_DA | DF_UB | DF_FP_B | DF_CORE_A,
 
   // 88 FLOAT_TO_LONG vA, vB
-  DF_DA_WIDE | DF_UB | DF_FP_B | DF_CORE_A,
+  DF_DA | DF_A_WIDE | DF_UB | DF_FP_B | DF_CORE_A,
 
   // 89 FLOAT_TO_DOUBLE vA, vB
-  DF_DA_WIDE | DF_UB | DF_FP_A | DF_FP_B,
+  DF_DA | DF_A_WIDE | DF_UB | DF_FP_A | DF_FP_B,
 
   // 8A DOUBLE_TO_INT vA, vB
-  DF_DA | DF_UB_WIDE | DF_FP_B | DF_CORE_A,
+  DF_DA | DF_UB | DF_B_WIDE | DF_FP_B | DF_CORE_A,
 
   // 8B DOUBLE_TO_LONG vA, vB
-  DF_DA_WIDE | DF_UB_WIDE | DF_FP_B | DF_CORE_A,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_B | DF_CORE_A,
 
   // 8C DOUBLE_TO_FLOAT vA, vB
-  DF_DA | DF_UB_WIDE | DF_FP_A | DF_FP_B,
+  DF_DA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
 
   // 8D INT_TO_BYTE vA, vB
   DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
@@ -463,10 +463,10 @@ const int oatDataFlowAttributes[kMirOpLast] = {
   DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
   // 90 ADD_INT vAA, vBB, vCC
-  DF_DA | DF_UB | DF_UC | DF_IS_LINEAR | DF_CORE_A | DF_CORE_B | DF_CORE_C,
+  DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
   // 91 SUB_INT vAA, vBB, vCC
-  DF_DA | DF_UB | DF_UC | DF_IS_LINEAR | DF_CORE_A | DF_CORE_B | DF_CORE_C,
+  DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
   // 92 MUL_INT vAA, vBB, vCC
   DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
@@ -496,37 +496,37 @@ const int oatDataFlowAttributes[kMirOpLast] = {
   DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
   // 9B ADD_LONG vAA, vBB, vCC
-  DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
   // 9C SUB_LONG vAA, vBB, vCC
-  DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
   // 9D MUL_LONG vAA, vBB, vCC
-  DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
   // 9E DIV_LONG vAA, vBB, vCC
-  DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
   // 9F REM_LONG vAA, vBB, vCC
-  DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
   // A0 AND_LONG vAA, vBB, vCC
-  DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
   // A1 OR_LONG vAA, vBB, vCC
-  DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
   // A2 XOR_LONG vAA, vBB, vCC
-  DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
   // A3 SHL_LONG vAA, vBB, vCC
-  DF_DA_WIDE | DF_UB_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
   // A4 SHR_LONG vAA, vBB, vCC
-  DF_DA_WIDE | DF_UB_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
   // A5 USHR_LONG vAA, vBB, vCC
-  DF_DA_WIDE | DF_UB_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
 
   // A6 ADD_FLOAT vAA, vBB, vCC
   DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
@@ -544,19 +544,19 @@ const int oatDataFlowAttributes[kMirOpLast] = {
   DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
 
   // AB ADD_DOUBLE vAA, vBB, vCC
-  DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
 
   // AC SUB_DOUBLE vAA, vBB, vCC
-  DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
 
   // AD MUL_DOUBLE vAA, vBB, vCC
-  DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
 
   // AE DIV_DOUBLE vAA, vBB, vCC
-  DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
 
   // AF REM_DOUBLE vAA, vBB, vCC
-  DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
+  DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
 
   // B0 ADD_INT_2ADDR vA, vB
   DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
@@ -592,37 +592,37 @@ const int oatDataFlowAttributes[kMirOpLast] = {
   DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
 
   // BB ADD_LONG_2ADDR vA, vB
-  DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
+  DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
 
   // BC SUB_LONG_2ADDR vA, vB
-  DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
+  DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
 
   // BD MUL_LONG_2ADDR vA, vB
-  DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
+  DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
 
   // BE DIV_LONG_2ADDR vA, vB
-  DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
+  DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
 
   // BF REM_LONG_2ADDR vA, vB
-  DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
+  DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
 
   // C0 AND_LONG_2ADDR vA, vB
-  DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
+  DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
 
   // C1 OR_LONG_2ADDR vA, vB
-  DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
+  DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
 
   // C2 XOR_LONG_2ADDR vA, vB
-  DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
+  DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
 
   // C3 SHL_LONG_2ADDR vA, vB
-  DF_DA_WIDE | DF_UA_WIDE | DF_UB | DF_CORE_A | DF_CORE_B,
+  DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
 
   // C4 SHR_LONG_2ADDR vA, vB
-  DF_DA_WIDE | DF_UA_WIDE | DF_UB | DF_CORE_A | DF_CORE_B,
+  DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
 
   // C5 USHR_LONG_2ADDR vA, vB
-  DF_DA_WIDE | DF_UA_WIDE | DF_UB | DF_CORE_A | DF_CORE_B,
+  DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
 
   // C6 ADD_FLOAT_2ADDR vA, vB
   DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
@@ -640,19 +640,19 @@ const int oatDataFlowAttributes[kMirOpLast] = {
   DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
 
   // CB ADD_DOUBLE_2ADDR vA, vB
-  DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
+  DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
 
   // CC SUB_DOUBLE_2ADDR vA, vB
-  DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
+  DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
 
   // CD MUL_DOUBLE_2ADDR vA, vB
-  DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
+  DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
 
   // CE DIV_DOUBLE_2ADDR vA, vB
-  DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
+  DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
 
   // CF REM_DOUBLE_2ADDR vA, vB
-  DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
+  DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
 
   // D0 ADD_INT_LIT16 vA, vB, #+CCCC
   DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
@@ -679,7 +679,7 @@ const int oatDataFlowAttributes[kMirOpLast] = {
   DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
   // D8 ADD_INT_LIT8 vAA, vBB, #+CC
-  DF_DA | DF_UB | DF_IS_LINEAR | DF_CORE_A | DF_CORE_B,
+  DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
   // D9 RSUB_INT_LIT8 vAA, vBB, #+CC
   DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
@@ -712,10 +712,10 @@ const int oatDataFlowAttributes[kMirOpLast] = {
   DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
 
   // E3 IGET_VOLATILE
-  DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_B,
+  DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
 
   // E4 IPUT_VOLATILE
-  DF_UA | DF_UB | DF_NULL_CHK_1 | DF_CORE_B,
+  DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B,
 
   // E5 SGET_VOLATILE
   DF_DA | DF_UMS,
@@ -724,19 +724,19 @@ const int oatDataFlowAttributes[kMirOpLast] = {
   DF_UA | DF_UMS,
 
   // E7 IGET_OBJECT_VOLATILE
-  DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_A | DF_CORE_B,
+  DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_A | DF_REF_B,
 
   // E8 IGET_WIDE_VOLATILE
-  DF_DA_WIDE | DF_UB | DF_NULL_CHK_0 | DF_CORE_B,
+  DF_DA | DF_A_WIDE | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
 
   // E9 IPUT_WIDE_VOLATILE
-  DF_UA_WIDE | DF_UB | DF_NULL_CHK_2 | DF_CORE_B,
+  DF_UA | DF_A_WIDE | DF_UB | DF_NULL_CHK_2 | DF_REF_B,
 
   // EA SGET_WIDE_VOLATILE
-  DF_DA_WIDE | DF_UMS,
+  DF_DA | DF_A_WIDE | DF_UMS,
 
   // EB SPUT_WIDE_VOLATILE
-  DF_UA_WIDE | DF_UMS,
+  DF_UA | DF_A_WIDE | DF_UMS,
 
   // EC BREAKPOINT
   DF_NOP,
@@ -760,7 +760,7 @@ const int oatDataFlowAttributes[kMirOpLast] = {
   DF_DA | DF_UB | DF_NULL_CHK_0,
 
   // F3 IGET_WIDE_QUICK
-  DF_DA_WIDE | DF_UB | DF_NULL_CHK_0,
+  DF_DA | DF_A_WIDE | DF_UB | DF_NULL_CHK_0,
 
   // F4 IGET_OBJECT_QUICK
   DF_DA | DF_UB | DF_NULL_CHK_0,
@@ -769,7 +769,7 @@ const int oatDataFlowAttributes[kMirOpLast] = {
   DF_UA | DF_UB | DF_NULL_CHK_1,
 
   // F6 IPUT_WIDE_QUICK
-  DF_UA_WIDE | DF_UB | DF_NULL_CHK_2,
+  DF_UA | DF_A_WIDE | DF_UB | DF_NULL_CHK_2,
 
   // F7 IPUT_OBJECT_QUICK
   DF_UA | DF_UB | DF_NULL_CHK_1,
@@ -787,20 +787,20 @@ const int oatDataFlowAttributes[kMirOpLast] = {
   DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
 
   // FC IPUT_OBJECT_VOLATILE
-  DF_UA | DF_UB | DF_NULL_CHK_1 | DF_CORE_A | DF_CORE_B,
+  DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_A | DF_REF_B,
 
   // FD SGET_OBJECT_VOLATILE
-  DF_DA | DF_CORE_A | DF_UMS,
+  DF_DA | DF_REF_A | DF_UMS,
 
   // FE SPUT_OBJECT_VOLATILE
-  DF_UA | DF_CORE_A | DF_UMS,
+  DF_UA | DF_REF_A | DF_UMS,
 
   // FF UNUSED_FF
   DF_NOP,
 
   // Beginning of extended MIR opcodes
   // 100 MIR_PHI
-  DF_PHI | DF_DA | DF_NULL_TRANSFER_N,
+  DF_DA | DF_NULL_TRANSFER_N,
 
   // 101 MIR_COPY
   DF_DA | DF_UB | DF_IS_MOVE,
@@ -812,13 +812,13 @@ const int oatDataFlowAttributes[kMirOpLast] = {
   DF_UA | DF_UB | DF_FP_A | DF_FP_B,
 
   // 104 MIR_FUSED_CMPL_DOUBLE
-  DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
+  DF_UA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
 
   // 105 MIR_FUSED_CMPG_DOUBLE
-  DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
+  DF_UA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
 
   // 106 MIR_FUSED_CMP_LONG
-  DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
+  DF_UA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
 
   // 107 MIR_NOP
   DF_NOP,
@@ -1140,21 +1140,21 @@ bool oatFindLocalLiveIn(CompilationUnit* cUnit, BasicBlock* bb)
     if (dfAttributes & DF_HAS_USES) {
       if (dfAttributes & DF_UA) {
         handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vA);
-      } else if (dfAttributes & DF_UA_WIDE) {
-        handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vA);
-        handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vA+1);
+        if (dfAttributes & DF_A_WIDE) {
+          handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vA+1);
+        }
       }
       if (dfAttributes & DF_UB) {
         handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vB);
-      } else if (dfAttributes & DF_UB_WIDE) {
-        handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vB);
-        handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vB+1);
+        if (dfAttributes & DF_B_WIDE) {
+          handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vB+1);
+        }
       }
       if (dfAttributes & DF_UC) {
         handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vC);
-      } else if (dfAttributes & DF_UC_WIDE) {
-        handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vC);
-        handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vC+1);
+        if (dfAttributes & DF_C_WIDE) {
+          handleLiveInUse(cUnit, useV, defV, liveInV, dInsn->vC+1);
+        }
       }
     }
     if (dfAttributes & DF_FORMAT_35C) {
@@ -1169,7 +1169,7 @@ bool oatFindLocalLiveIn(CompilationUnit* cUnit, BasicBlock* bb)
     }
     if (dfAttributes & DF_HAS_DEFS) {
       handleDef(cUnit, defV, dInsn->vA);
-      if (dfAttributes & DF_DA_WIDE) {
+      if (dfAttributes & DF_A_WIDE) {
         handleDef(cUnit, defV, dInsn->vA+1);
       }
     }
@@ -1286,18 +1286,21 @@ bool oatDoSSAConversion(CompilationUnit* cUnit, BasicBlock* bb)
     if (dfAttributes & DF_HAS_USES) {
       if (dfAttributes & DF_UA) {
         numUses++;
-      } else if (dfAttributes & DF_UA_WIDE) {
-        numUses += 2;
+        if (dfAttributes & DF_A_WIDE) {
+          numUses ++;
+        }
       }
       if (dfAttributes & DF_UB) {
         numUses++;
-      } else if (dfAttributes & DF_UB_WIDE) {
-        numUses += 2;
+        if (dfAttributes & DF_B_WIDE) {
+          numUses ++;
+        }
       }
       if (dfAttributes & DF_UC) {
         numUses++;
-      } else if (dfAttributes & DF_UC_WIDE) {
-        numUses += 2;
+        if (dfAttributes & DF_C_WIDE) {
+          numUses ++;
+        }
       }
     }
 
@@ -1313,7 +1316,7 @@ bool oatDoSSAConversion(CompilationUnit* cUnit, BasicBlock* bb)
 
     if (dfAttributes & DF_HAS_DEFS) {
       numDefs++;
-      if (dfAttributes & DF_DA_WIDE) {
+      if (dfAttributes & DF_A_WIDE) {
         numDefs++;
       }
     }
@@ -1333,35 +1336,32 @@ bool oatDoSSAConversion(CompilationUnit* cUnit, BasicBlock* bb)
       if (dfAttributes & DF_UA) {
         mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_A;
         handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vA, numUses++);
-      } else if (dfAttributes & DF_UA_WIDE) {
-        mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_A;
-        handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vA, numUses++);
-        mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_A;
-        handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vA+1, numUses++);
+        if (dfAttributes & DF_A_WIDE) {
+          mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_A;
+          handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vA+1, numUses++);
+        }
       }
       if (dfAttributes & DF_UB) {
         mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_B;
         handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vB, numUses++);
-      } else if (dfAttributes & DF_UB_WIDE) {
-        mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_B;
-        handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vB, numUses++);
-        mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_B;
-        handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vB+1, numUses++);
+        if (dfAttributes & DF_B_WIDE) {
+          mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_B;
+          handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vB+1, numUses++);
+        }
       }
       if (dfAttributes & DF_UC) {
         mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_C;
         handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vC, numUses++);
-      } else if (dfAttributes & DF_UC_WIDE) {
-        mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_C;
-        handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vC, numUses++);
-        mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_C;
-        handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vC+1, numUses++);
+        if (dfAttributes & DF_C_WIDE) {
+          mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_C;
+          handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vC+1, numUses++);
+        }
       }
     }
     if (dfAttributes & DF_HAS_DEFS) {
       mir->ssaRep->fpDef[0] = dfAttributes & DF_FP_A;
       handleSSADef(cUnit, mir->ssaRep->defs, dInsn->vA, 0);
-      if (dfAttributes & DF_DA_WIDE) {
+      if (dfAttributes & DF_A_WIDE) {
         mir->ssaRep->fpDef[1] = dfAttributes & DF_FP_A;
         handleSSADef(cUnit, mir->ssaRep->defs, dInsn->vA+1, 1);
       }
@@ -1415,29 +1415,24 @@ bool oatDoConstantPropagation(CompilationUnit* cUnit, BasicBlock* bb)
           case Instruction::CONST_HIGH16:
             setConstant(cUnit, mir->ssaRep->defs[0], dInsn->vB << 16);
             break;
+          case Instruction::CONST_WIDE_16:
+          case Instruction::CONST_WIDE_32:
+            setConstant(cUnit, mir->ssaRep->defs[0], dInsn->vB);
+            setConstant(cUnit, mir->ssaRep->defs[1], 0);
+            break;
+          case Instruction::CONST_WIDE:
+            setConstant(cUnit, mir->ssaRep->defs[0], (int) dInsn->vB_wide);
+            setConstant(cUnit, mir->ssaRep->defs[1],
+                        (int) (dInsn->vB_wide >> 32));
+            break;
+          case Instruction::CONST_WIDE_HIGH16:
+            setConstant(cUnit, mir->ssaRep->defs[0], 0);
+            setConstant(cUnit, mir->ssaRep->defs[1], dInsn->vB << 16);
+            break;
           default:
             break;
-              }
-          } else if (dfAttributes & DF_DA_WIDE) {
-            switch (dInsn->opcode) {
-              case Instruction::CONST_WIDE_16:
-              case Instruction::CONST_WIDE_32:
-                setConstant(cUnit, mir->ssaRep->defs[0], dInsn->vB);
-                setConstant(cUnit, mir->ssaRep->defs[1], 0);
-                break;
-              case Instruction::CONST_WIDE:
-                setConstant(cUnit, mir->ssaRep->defs[0], (int) dInsn->vB_wide);
-                setConstant(cUnit, mir->ssaRep->defs[1],
-                            (int) (dInsn->vB_wide >> 32));
-                break;
-              case Instruction::CONST_WIDE_HIGH16:
-                setConstant(cUnit, mir->ssaRep->defs[0], 0);
-                setConstant(cUnit, mir->ssaRep->defs[1], dInsn->vB << 16);
-                break;
-              default:
-                break;
-            }
           }
+        }
       /* Handle instructions that set up constants directly */
       } else if (dfAttributes & DF_IS_MOVE) {
         int i;
@@ -1449,7 +1444,7 @@ bool oatDoConstantPropagation(CompilationUnit* cUnit, BasicBlock* bb)
       if (i == mir->ssaRep->numUses) {
         setConstant(cUnit, mir->ssaRep->defs[0],
                     cUnit->constantValues[mir->ssaRep->uses[0]]);
-        if (dfAttributes & DF_DA_WIDE) {
+        if (dfAttributes & DF_A_WIDE) {
           setConstant(cUnit, mir->ssaRep->defs[1],
                       cUnit->constantValues[mir->ssaRep->uses[1]]);
         }
diff --git a/src/compiler/Dataflow.h b/src/compiler/Dataflow.h
index 941b544c11..9ac54d59e5 100644
--- a/src/compiler/Dataflow.h
+++ b/src/compiler/Dataflow.h
@@ -26,17 +26,14 @@ enum DataFlowAttributePos {
   kUA = 0,
   kUB,
   kUC,
-  kUAWide,
-  kUBWide,
-  kUCWide,
+  kAWide,
+  kBWide,
+  kCWide,
   kDA,
-  kDAWide,
   kIsMove,
-  kIsLinear,
   kSetsConst,
   kFormat35c,
   kFormat3rc,
-  kPhi,
   kNullCheckSrc0,        // Null check of uses[0]
   kNullCheckSrc1,        // Null check of uses[1]
   kNullCheckSrc2,        // Null check of uses[2]
@@ -54,6 +51,9 @@ enum DataFlowAttributePos {
   kCoreA,
   kCoreB,
   kCoreC,
+  kRefA,
+  kRefB,
+  kRefC,
   kUsesMethodStar,       // Implicit use of Method*
 };
 
@@ -61,17 +61,14 @@ enum DataFlowAttributePos {
 #define DF_UA                   (1 << kUA)
 #define DF_UB                   (1 << kUB)
 #define DF_UC                   (1 << kUC)
-#define DF_UA_WIDE              (1 << kUAWide)
-#define DF_UB_WIDE              (1 << kUBWide)
-#define DF_UC_WIDE              (1 << kUCWide)
+#define DF_A_WIDE               (1 << kAWide)
+#define DF_B_WIDE               (1 << kBWide)
+#define DF_C_WIDE               (1 << kCWide)
 #define DF_DA                   (1 << kDA)
-#define DF_DA_WIDE              (1 << kDAWide)
 #define DF_IS_MOVE              (1 << kIsMove)
-#define DF_IS_LINEAR            (1 << kIsLinear)
 #define DF_SETS_CONST           (1 << kSetsConst)
 #define DF_FORMAT_35C           (1 << kFormat35c)
 #define DF_FORMAT_3RC           (1 << kFormat3rc)
-#define DF_PHI                  (1 << kPhi)
 #define DF_NULL_CHK_0           (1 << kNullCheckSrc0)
 #define DF_NULL_CHK_1           (1 << kNullCheckSrc1)
 #define DF_NULL_CHK_2           (1 << kNullCheckSrc2)
@@ -89,12 +86,14 @@ enum DataFlowAttributePos {
 #define DF_CORE_A               (1 << kCoreA)
 #define DF_CORE_B               (1 << kCoreB)
 #define DF_CORE_C               (1 << kCoreC)
+#define DF_REF_A                (1 << kRefA)
+#define DF_REF_B                (1 << kRefB)
+#define DF_REF_C                (1 << kRefC)
 #define DF_UMS                  (1 << kUsesMethodStar)
 
-#define DF_HAS_USES             (DF_UA | DF_UB | DF_UC | DF_UA_WIDE | \
-                                 DF_UB_WIDE | DF_UC_WIDE)
+#define DF_HAS_USES             (DF_UA | DF_UB | DF_UC)
 
-#define DF_HAS_DEFS             (DF_DA | DF_DA_WIDE)
+#define DF_HAS_DEFS             (DF_DA)
 
 #define DF_HAS_NULL_CHKS        (DF_NULL_CHK_0 | \
                                  DF_NULL_CHK_1 | \
@@ -105,9 +104,9 @@ enum DataFlowAttributePos {
                                  DF_RANGE_CHK_1 | \
                                  DF_RANGE_CHK_2)
 
-#define DF_A_IS_REG             (DF_UA | DF_UA_WIDE | DF_DA | DF_DA_WIDE)
-#define DF_B_IS_REG             (DF_UB | DF_UB_WIDE)
-#define DF_C_IS_REG             (DF_UC | DF_UC_WIDE)
+#define DF_A_IS_REG             (DF_UA | DF_DA)
+#define DF_B_IS_REG             (DF_UB)
+#define DF_C_IS_REG             (DF_UC)
 #define DF_IS_GETTER_OR_SETTER  (DF_IS_GETTER | DF_IS_SETTER)
 #define DF_USES_FP              (DF_FP_A | DF_FP_B | DF_FP_C)
 
diff --git a/src/compiler/Frontend.cc b/src/compiler/Frontend.cc
index dce9b8bd14..5365d4afb4 100644
--- a/src/compiler/Frontend.cc
+++ b/src/compiler/Frontend.cc
@@ -913,7 +913,7 @@ CompiledMethod* oatCompileMethod(Compiler& compiler,
     int dfFlags = oatDataFlowAttributes[insn->dalvikInsn.opcode];
 
     if (dfFlags & DF_HAS_DEFS) {
-      cUnit->defCount += (dfFlags & DF_DA_WIDE) ? 2 : 1;
+      cUnit->defCount += (dfFlags & DF_A_WIDE) ? 2 : 1;
     }
 
     if (flags & Instruction::kBranch) {
diff --git a/src/compiler/Ralloc.cc b/src/compiler/Ralloc.cc
index 54728db607..480a96de9b 100644
--- a/src/compiler/Ralloc.cc
+++ b/src/compiler/Ralloc.cc
@@ -47,6 +47,19 @@ bool setCore(CompilationUnit* cUnit, int index, bool isCore) {
   return change;
 }
 
+bool setRef(CompilationUnit* cUnit, int index, bool isRef) {
+  bool change = false;
+  if (cUnit->regLocation[index].highWord) {
+    return change;
+  }
+  if (isRef && !cUnit->regLocation[index].defined) {
+    cUnit->regLocation[index].ref = true;
+    cUnit->regLocation[index].defined = true;
+    change = true;
+  }
+  return change;
+}
+
 bool remapNames(CompilationUnit* cUnit, BasicBlock* bb)
 {
   if (bb->blockType != kDalvikByteCode && bb->blockType != kEntryBlock &&
@@ -101,11 +114,14 @@ bool inferTypeAndSize(CompilationUnit* cUnit, BasicBlock* bb)
       int attrs = oatDataFlowAttributes[mir->dalvikInsn.opcode];
 
       // Handle defs
-      if (attrs & (DF_DA | DF_DA_WIDE)) {
+      if (attrs & DF_DA) {
         if (attrs & DF_CORE_A) {
           changed |= setCore(cUnit, ssaRep->defs[0], true);
         }
-        if (attrs & DF_DA_WIDE) {
+        if (attrs & DF_REF_A) {
+          changed |= setRef(cUnit, ssaRep->defs[0], true);
+        }
+        if (attrs & DF_A_WIDE) {
           cUnit->regLocation[ssaRep->defs[0]].wide = true;
           cUnit->regLocation[ssaRep->defs[1]].highWord = true;
           DCHECK_EQ(SRegToVReg(cUnit, ssaRep->defs[0])+1,
@@ -115,11 +131,14 @@ bool inferTypeAndSize(CompilationUnit* cUnit, BasicBlock* bb)
 
       // Handles uses
       int next = 0;
-      if (attrs & (DF_UA | DF_UA_WIDE)) {
+      if (attrs & DF_UA) {
         if (attrs & DF_CORE_A) {
           changed |= setCore(cUnit, ssaRep->uses[next], true);
         }
-        if (attrs & DF_UA_WIDE) {
+        if (attrs & DF_REF_A) {
+          changed |= setRef(cUnit, ssaRep->uses[next], true);
+        }
+        if (attrs & DF_A_WIDE) {
           cUnit->regLocation[ssaRep->uses[next]].wide = true;
           cUnit->regLocation[ssaRep->uses[next + 1]].highWord = true;
           DCHECK_EQ(SRegToVReg(cUnit, ssaRep->uses[next])+1,
@@ -129,11 +148,14 @@ bool inferTypeAndSize(CompilationUnit* cUnit, BasicBlock* bb)
           next++;
         }
       }
-      if (attrs & (DF_UB | DF_UB_WIDE)) {
+      if (attrs & DF_UB) {
         if (attrs & DF_CORE_B) {
           changed |= setCore(cUnit, ssaRep->uses[next], true);
         }
-        if (attrs & DF_UB_WIDE) {
+        if (attrs & DF_REF_B) {
+          changed |= setRef(cUnit, ssaRep->uses[next], true);
+        }
+        if (attrs & DF_B_WIDE) {
           cUnit->regLocation[ssaRep->uses[next]].wide = true;
           cUnit->regLocation[ssaRep->uses[next + 1]].highWord = true;
           DCHECK_EQ(SRegToVReg(cUnit, ssaRep->uses[next])+1,
@@ -143,11 +165,14 @@ bool inferTypeAndSize(CompilationUnit* cUnit, BasicBlock* bb)
           next++;
         }
       }
-      if (attrs & (DF_UC | DF_UC_WIDE)) {
+      if (attrs & DF_UC) {
         if (attrs & DF_CORE_C) {
           changed |= setCore(cUnit, ssaRep->uses[next], true);
         }
-        if (attrs & DF_UC_WIDE) {
+        if (attrs & DF_REF_C) {
+          changed |= setRef(cUnit, ssaRep->uses[next], true);
+        }
+        if (attrs & DF_C_WIDE) {
           cUnit->regLocation[ssaRep->uses[next]].wide = true;
           cUnit->regLocation[ssaRep->uses[next + 1]].highWord = true;
           DCHECK_EQ(SRegToVReg(cUnit, ssaRep->uses[next])+1,
@@ -183,11 +208,11 @@ bool inferTypeAndSize(CompilationUnit* cUnit, BasicBlock* bb)
           }
         }
         int numUses = mir->dalvikInsn.vA;
-        // If this is a non-static invoke, skip implicit "this"
+        // If this is a non-static invoke, mark implicit "this"
         if (((mir->dalvikInsn.opcode != Instruction::INVOKE_STATIC) &&
             (mir->dalvikInsn.opcode != Instruction::INVOKE_STATIC_RANGE))) {
           cUnit->regLocation[ssaRep->uses[next]].defined = true;
-          cUnit->regLocation[ssaRep->uses[next]].core = true;
+          cUnit->regLocation[ssaRep->uses[next]].ref = true;
           next++;
         }
         uint32_t cpos = 1;
@@ -215,6 +240,9 @@ bool inferTypeAndSize(CompilationUnit* cUnit, BasicBlock* bb)
               case 'F':
                 ssaRep->fpUse[i] = true;
                 break;
+              case 'L':
+                changed |= setRef(cUnit,ssaRep->uses[i], true);
+                break;
               default:
                 changed |= setCore(cUnit,ssaRep->uses[i], true);
                 break;
@@ -237,15 +265,20 @@ bool inferTypeAndSize(CompilationUnit* cUnit, BasicBlock* bb)
         // If any of our inputs or outputs is defined, set all
         bool definedFP = false;
         bool definedCore = false;
+        bool definedRef = false;
         definedFP |= (cUnit->regLocation[ssaRep->defs[0]].defined &&
                       cUnit->regLocation[ssaRep->defs[0]].fp);
         definedCore |= (cUnit->regLocation[ssaRep->defs[0]].defined &&
                         cUnit->regLocation[ssaRep->defs[0]].core);
+        definedRef |= (cUnit->regLocation[ssaRep->defs[0]].defined &&
+                       cUnit->regLocation[ssaRep->defs[0]].ref);
         for (int i = 0; i < ssaRep->numUses; i++) {
           definedFP |= (cUnit->regLocation[ssaRep->uses[i]].defined &&
                         cUnit->regLocation[ssaRep->uses[i]].fp);
           definedCore |= (cUnit->regLocation[ssaRep->uses[i]].defined
                           && cUnit->regLocation[ssaRep->uses[i]].core);
+          definedRef |= (cUnit->regLocation[ssaRep->uses[i]].defined
+                         && cUnit->regLocation[ssaRep->uses[i]].ref);
         }
         /*
          * TODO: cleaner fix
@@ -261,18 +294,20 @@ bool inferTypeAndSize(CompilationUnit* cUnit, BasicBlock* bb)
          * disable register promotion (which is the only thing that
          * relies on distinctions between core and fp usages.
          */
-        if ((definedFP && definedCore) &&
+        if ((definedFP && (definedCore | definedRef)) &&
             ((cUnit->disableOpt & (1 << kPromoteRegs)) == 0)) {
           LOG(WARNING) << PrettyMethod(cUnit->method_idx, *cUnit->dex_file)
                        << " op at block " << bb->id
-                       << " has both fp and core uses for same def.";
+                       << " has both fp and core/ref uses for same def.";
           cUnit->disableOpt |= (1 << kPromoteRegs);
         }
         changed |= setFp(cUnit, ssaRep->defs[0], definedFP);
         changed |= setCore(cUnit, ssaRep->defs[0], definedCore);
+        changed |= setRef(cUnit, ssaRep->defs[0], definedRef);
         for (int i = 0; i < ssaRep->numUses; i++) {
          changed |= setFp(cUnit, ssaRep->uses[i], definedFP);
          changed |= setCore(cUnit, ssaRep->uses[i], definedCore);
+         changed |= setRef(cUnit, ssaRep->uses[i], definedRef);
         }
       }
     }
@@ -296,7 +331,7 @@ void oatDumpRegLocTable(RegLocation* table, int count)
   }
 }
 
-static const RegLocation freshLoc = {kLocDalvikFrame, 0, 0, 0, 0, 0, 0,
+static const RegLocation freshLoc = {kLocDalvikFrame, 0, 0, 0, 0, 0, 0, 0,
                                      INVALID_REG, INVALID_REG, INVALID_SREG};
 
 /*
@@ -343,7 +378,7 @@ void oatSimpleRegAlloc(CompilationUnit* cUnit)
     if ((cUnit->access_flags & kAccStatic) == 0) {
       // For non-static, skip past "this"
       cUnit->regLocation[sReg].defined = true;
-      cUnit->regLocation[sReg].core = true;
+      cUnit->regLocation[sReg].ref = true;
       sReg++;
     }
     const char* shorty = cUnit->shorty;
diff --git a/src/compiler/codegen/MethodCodegenDriver.cc b/src/compiler/codegen/MethodCodegenDriver.cc
index 8d6bf547d0..b75b9a88b9 100644
--- a/src/compiler/codegen/MethodCodegenDriver.cc
+++ b/src/compiler/codegen/MethodCodegenDriver.cc
@@ -21,7 +21,7 @@ namespace art {
 #define DISPLAY_MISSING_TARGETS (cUnit->enableDebug & \
                                  (1 << kDebugDisplayMissingTargets))
 
-const RegLocation badLoc = {kLocDalvikFrame, 0, 0, 0, 0, 0, 0,
+const RegLocation badLoc = {kLocDalvikFrame, 0, 0, 0, 0, 0, 0, 0,
                             INVALID_REG, INVALID_REG, INVALID_SREG};
 
 /* Mark register usage state and return long retloc */
@@ -179,30 +179,37 @@ bool compileDalvikInstruction(CompilationUnit* cUnit, MIR* mir,
   int attrs = oatDataFlowAttributes[opcode];
   rlSrc[0] = rlSrc[1] = rlSrc[2] = badLoc;
   if (attrs & DF_UA) {
-    rlSrc[nextLoc++] = oatGetSrc(cUnit, mir, nextSreg);
-    nextSreg++;
-  } else if (attrs & DF_UA_WIDE) {
-    rlSrc[nextLoc++] = oatGetSrcWide(cUnit, mir, nextSreg, nextSreg + 1);
-    nextSreg+= 2;
+    if (attrs & DF_A_WIDE) {
+      rlSrc[nextLoc++] = oatGetSrcWide(cUnit, mir, nextSreg, nextSreg + 1);
+      nextSreg+= 2;
+    } else {
+      rlSrc[nextLoc++] = oatGetSrc(cUnit, mir, nextSreg);
+      nextSreg++;
+    }
   }
   if (attrs & DF_UB) {
-    rlSrc[nextLoc++] = oatGetSrc(cUnit, mir, nextSreg);
-    nextSreg++;
-  } else if (attrs & DF_UB_WIDE) {
-    rlSrc[nextLoc++] = oatGetSrcWide(cUnit, mir, nextSreg, nextSreg + 1);
-    nextSreg+= 2;
+    if (attrs & DF_B_WIDE) {
+      rlSrc[nextLoc++] = oatGetSrcWide(cUnit, mir, nextSreg, nextSreg + 1);
+      nextSreg+= 2;
+    } else {
+      rlSrc[nextLoc++] = oatGetSrc(cUnit, mir, nextSreg);
+      nextSreg++;
+    }
   }
   if (attrs & DF_UC) {
-    rlSrc[nextLoc++] = oatGetSrc(cUnit, mir, nextSreg);
-  } else if (attrs & DF_UC_WIDE) {
-    rlSrc[nextLoc++] = oatGetSrcWide(cUnit, mir, nextSreg, nextSreg + 1);
+    if (attrs & DF_C_WIDE) {
+      rlSrc[nextLoc++] = oatGetSrcWide(cUnit, mir, nextSreg, nextSreg + 1);
+    } else {
+      rlSrc[nextLoc++] = oatGetSrc(cUnit, mir, nextSreg);
+    }
   }
   if (attrs & DF_DA) {
-    rlDest = oatGetDest(cUnit, mir, 0);
-  } else if (attrs & DF_DA_WIDE) {
-    rlDest = oatGetDestWide(cUnit, mir, 0, 1);
+    if (attrs & DF_A_WIDE) {
+      rlDest = oatGetDestWide(cUnit, mir, 0, 1);
+    } else {
+      rlDest = oatGetDest(cUnit, mir, 0);
+    }
   }
-
   switch (opcode) {
     case Instruction::NOP:
       break;
diff --git a/src/compiler/codegen/arm/ArmLIR.h b/src/compiler/codegen/arm/ArmLIR.h
index fc5aa40178..93e7878d54 100644
--- a/src/compiler/codegen/arm/ArmLIR.h
+++ b/src/compiler/codegen/arm/ArmLIR.h
@@ -125,9 +125,10 @@ namespace art {
 #define rNone   (-1)
 
 /* RegisterLocation templates return values (r0, or r0/r1) */
-#define LOC_C_RETURN {kLocPhysReg, 0, 0, 0, 0, 0, 1, r0, INVALID_REG,\
+#define LOC_C_RETURN {kLocPhysReg, 0, 0, 0, 0, 0, 0, 1, r0, INVALID_REG,\
+                      INVALID_SREG}
+#define LOC_C_RETURN_WIDE {kLocPhysReg, 1, 0, 0, 0, 0, 0, 1, r0, r1, \
                       INVALID_SREG}
-#define LOC_C_RETURN_WIDE {kLocPhysReg, 1, 0, 0, 0, 0, 1, r0, r1, INVALID_SREG}
 #define LOC_C_RETURN_FLOAT  LOC_C_RETURN
 #define LOC_C_RETURN_WIDE_DOUBLE  LOC_C_RETURN_WIDE
 
diff --git a/src/compiler/codegen/mips/MipsLIR.h b/src/compiler/codegen/mips/MipsLIR.h
index ac222c456f..c9f917b4a6 100644
--- a/src/compiler/codegen/mips/MipsLIR.h
+++ b/src/compiler/codegen/mips/MipsLIR.h
@@ -145,16 +145,16 @@ namespace art {
 #define r_FRESULT1 r_F1
 
 /* RegisterLocation templates return values (r_V0, or r_V0/r_V1) */
-#define LOC_C_RETURN {kLocPhysReg, 0, 0, 0, 0, 0, 1, r_V0, INVALID_REG, \
-            INVALID_SREG}
+#define LOC_C_RETURN {kLocPhysReg, 0, 0, 0, 0, 0, 0, 1, r_V0, INVALID_REG, \
+                      INVALID_SREG}
 #define LOC_C_RETURN_FLOAT  LOC_C_RETURN
-#define LOC_C_RETURN_ALT {kLocPhysReg, 0, 0, 0, 0, 0, 1, r_F0, INVALID_REG, \
-              INVALID_SREG}
-#define LOC_C_RETURN_WIDE {kLocPhysReg, 1, 0, 0, 0, 0, 1, r_RESULT0, r_RESULT1,\
-               INVALID_SREG}
+#define LOC_C_RETURN_ALT {kLocPhysReg, 0, 0, 0, 0, 0, 0, 1, r_F0, INVALID_REG, \
+                          INVALID_SREG}
+#define LOC_C_RETURN_WIDE {kLocPhysReg, 1, 0, 0, 0, 0, 0, 1, r_RESULT0, \
+                           r_RESULT1, INVALID_SREG}
 #define LOC_C_RETURN_WIDE_DOUBLE  LOC_C_RETURN_WIDE
-#define LOC_C_RETURN_WIDE_ALT {kLocPhysReg, 1, 0, 0, 0, 0, 1, r_FRESULT0,\
-                 r_FRESULT1, INVALID_SREG}
+#define LOC_C_RETURN_WIDE_ALT {kLocPhysReg, 1, 0, 0, 0, 0, 0, 1, r_FRESULT0,\
+                               r_FRESULT1, INVALID_SREG}
 
 enum ResourceEncodingPos {
   kGPReg0   = 0,
diff --git a/src/compiler/codegen/x86/ArchFactory.cc b/src/compiler/codegen/x86/ArchFactory.cc
index dc1323817a..1d3893a760 100644
--- a/src/compiler/codegen/x86/ArchFactory.cc
+++ b/src/compiler/codegen/x86/ArchFactory.cc
@@ -34,7 +34,7 @@ bool genAddLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
   // Compute (r1:r0) = (r1:r0) + (r2:r3)
   opRegReg(cUnit, kOpAdd, r0, r2);  // r0 = r0 + r2
   opRegReg(cUnit, kOpAdc, r1, r3);  // r1 = r1 + r3 + CF
-  RegLocation rlResult = {kLocPhysReg, 1, 0, 0,  0, 0, 1, r0, r1, INVALID_SREG};
+  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 1, r0, r1, INVALID_SREG};
   storeValueWide(cUnit, rlDest, rlResult);
   return false;
 }
@@ -49,7 +49,7 @@ bool genSubLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
   // Compute (r1:r0) = (r1:r0) + (r2:r3)
   opRegReg(cUnit, kOpSub, r0, r2);  // r0 = r0 - r2
   opRegReg(cUnit, kOpSbc, r1, r3);  // r1 = r1 - r3 - CF
-  RegLocation rlResult = {kLocPhysReg, 1, 0, 0,  0, 0, 1, r0, r1, INVALID_SREG};
+  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 1, r0, r1, INVALID_SREG};
   storeValueWide(cUnit, rlDest, rlResult);
   return false;
 }
@@ -64,7 +64,7 @@ bool genAndLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
   // Compute (r1:r0) = (r1:r0) + (r2:r3)
   opRegReg(cUnit, kOpAnd, r0, r2);  // r0 = r0 - r2
   opRegReg(cUnit, kOpAnd, r1, r3);  // r1 = r1 - r3 - CF
-  RegLocation rlResult = {kLocPhysReg, 1, 0, 0,  0, 0, 1, r0, r1, INVALID_SREG};
+  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 1, r0, r1, INVALID_SREG};
   storeValueWide(cUnit, rlDest, rlResult);
   return false;
 }
@@ -79,7 +79,7 @@ bool genOrLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
   // Compute (r1:r0) = (r1:r0) + (r2:r3)
   opRegReg(cUnit, kOpOr, r0, r2);  // r0 = r0 - r2
   opRegReg(cUnit, kOpOr, r1, r3);  // r1 = r1 - r3 - CF
-  RegLocation rlResult = {kLocPhysReg, 1, 0, 0,  0, 0, 1, r0, r1, INVALID_SREG};
+  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 1, r0, r1, INVALID_SREG};
   storeValueWide(cUnit, rlDest, rlResult);
   return false;
 }
@@ -94,7 +94,7 @@ bool genXorLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
   // Compute (r1:r0) = (r1:r0) + (r2:r3)
   opRegReg(cUnit, kOpXor, r0, r2);  // r0 = r0 - r2
   opRegReg(cUnit, kOpXor, r1, r3);  // r1 = r1 - r3 - CF
-  RegLocation rlResult = {kLocPhysReg, 1, 0, 0,  0, 0, 1, r0, r1, INVALID_SREG};
+  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 1, r0, r1, INVALID_SREG};
   storeValueWide(cUnit, rlDest, rlResult);
   return false;
 }
@@ -109,7 +109,7 @@ bool genNegLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
   opRegReg(cUnit, kOpNeg, r0, r0);  // r0 = -r0
   opRegImm(cUnit, kOpAdc, r1, 0);   // r1 = r1 + CF
   opRegReg(cUnit, kOpNeg, r1, r1);  // r1 = -r1
-  RegLocation rlResult = {kLocPhysReg, 1, 0, 0,  0, 0, 1, r0, r1, INVALID_SREG};
+  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 1, r0, r1, INVALID_SREG};
   storeValueWide(cUnit, rlDest, rlResult);
   return false;
 }
diff --git a/src/compiler/codegen/x86/X86LIR.h b/src/compiler/codegen/x86/X86LIR.h
index 3646a1f7ef..36e459cf29 100644
--- a/src/compiler/codegen/x86/X86LIR.h
+++ b/src/compiler/codegen/x86/X86LIR.h
@@ -137,11 +137,11 @@ namespace art {
 #define rNone   (-1)
 
 /* RegisterLocation templates return values (rAX, rAX/rDX or XMM0) */
-//                               location,     wide, defined, fp, core, highWord, home, lowReg, highReg,     sRegLow
-#define LOC_C_RETURN             {kLocPhysReg, 0,    0,       0,  0,    0,        1,    rAX,    INVALID_REG, INVALID_SREG}
-#define LOC_C_RETURN_WIDE        {kLocPhysReg, 1,    0,       0,  0,    0,        1,    rAX,    rDX,         INVALID_SREG}
-#define LOC_C_RETURN_FLOAT       {kLocPhysReg, 0,    0,       1,  0,    0,        1,    fr0,    INVALID_REG, INVALID_SREG}
-#define LOC_C_RETURN_WIDE_DOUBLE {kLocPhysReg, 1,    0,       1,  0,    0,        1,    fr0,    fr1,         INVALID_SREG}
+//                               location,     wide, defined, fp, core, ref, highWord, home, lowReg, highReg,     sRegLow
+#define LOC_C_RETURN             {kLocPhysReg, 0,    0,       0,  0,    0,   0,        1,    rAX,    INVALID_REG, INVALID_SREG}
+#define LOC_C_RETURN_WIDE        {kLocPhysReg, 1,    0,       0,  0,    0,   0,        1,    rAX,    rDX,         INVALID_SREG}
+#define LOC_C_RETURN_FLOAT       {kLocPhysReg, 0,    0,       1,  0,    0,   0,        1,    fr0,    INVALID_REG, INVALID_SREG}
+#define LOC_C_RETURN_WIDE_DOUBLE {kLocPhysReg, 1,    0,       1,  0,    0,   0,        1,    fr0,    fr1,         INVALID_SREG}
 
 enum ResourceEncodingPos {
   kGPReg0   = 0,