diff options
| author | 2012-04-04 11:27:00 -0700 | |
|---|---|---|
| committer | 2012-04-04 11:27:00 -0700 | |
| commit | 99d067610dca2aab62b2a6b5578f5e5815811b2a (patch) | |
| tree | c71f07402ba4f01fbf9f8e40081ffd78ab47806b | |
| parent | 94347f2c6be1e0f7532b5e8f9831496d63f9db48 (diff) | |
| parent | fc700ed5af8d7c9ac044698b078a12a92a360ba7 (diff) | |
Merge "Fix x86 long math." into ics-mr1-plus-art
| -rw-r--r-- | src/compiler/codegen/x86/ArchFactory.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/compiler/codegen/x86/ArchFactory.cc b/src/compiler/codegen/x86/ArchFactory.cc index e6682505ef..043d66ee70 100644 --- a/src/compiler/codegen/x86/ArchFactory.cc +++ b/src/compiler/codegen/x86/ArchFactory.cc @@ -30,7 +30,7 @@ bool genAddLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest, oatFlushAllRegs(cUnit); oatLockCallTemps(cUnit); // Prepare for explicit register usage loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1); - loadValueDirectWideFixed(cUnit, rlSrc1, r2, r3); + loadValueDirectWideFixed(cUnit, rlSrc2, r2, r3); // Compute (r1:r0) = (r1:r0) + (r2:r3) opRegReg(cUnit, kOpAdd, r0, r2); // r0 = r0 + r2 opRegReg(cUnit, kOpAdc, r1, r3); // r1 = r1 + r3 + CF @@ -45,7 +45,7 @@ bool genSubLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest, oatFlushAllRegs(cUnit); oatLockCallTemps(cUnit); // Prepare for explicit register usage loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1); - loadValueDirectWideFixed(cUnit, rlSrc1, r2, r3); + loadValueDirectWideFixed(cUnit, rlSrc2, r2, r3); // Compute (r1:r0) = (r1:r0) + (r2:r3) opRegReg(cUnit, kOpSub, r0, r2); // r0 = r0 - r2 opRegReg(cUnit, kOpSbc, r1, r3); // r1 = r1 - r3 - CF @@ -60,7 +60,7 @@ bool genAndLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest, oatFlushAllRegs(cUnit); oatLockCallTemps(cUnit); // Prepare for explicit register usage loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1); - loadValueDirectWideFixed(cUnit, rlSrc1, r2, r3); + loadValueDirectWideFixed(cUnit, rlSrc2, r2, r3); // Compute (r1:r0) = (r1:r0) + (r2:r3) opRegReg(cUnit, kOpAnd, r0, r2); // r0 = r0 - r2 opRegReg(cUnit, kOpAnd, r1, r3); // r1 = r1 - r3 - CF @@ -75,7 +75,7 @@ bool genOrLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest, oatFlushAllRegs(cUnit); oatLockCallTemps(cUnit); // Prepare for explicit register usage loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1); - loadValueDirectWideFixed(cUnit, rlSrc1, r2, r3); + loadValueDirectWideFixed(cUnit, rlSrc2, r2, r3); // Compute (r1:r0) = (r1:r0) + (r2:r3) opRegReg(cUnit, kOpOr, r0, r2); // r0 = r0 - r2 opRegReg(cUnit, kOpOr, r1, r3); // r1 = r1 - r3 - CF @@ -90,7 +90,7 @@ bool genXorLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest, oatFlushAllRegs(cUnit); oatLockCallTemps(cUnit); // Prepare for explicit register usage loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1); - loadValueDirectWideFixed(cUnit, rlSrc1, r2, r3); + loadValueDirectWideFixed(cUnit, rlSrc2, r2, r3); // Compute (r1:r0) = (r1:r0) + (r2:r3) opRegReg(cUnit, kOpXor, r0, r2); // r0 = r0 - r2 opRegReg(cUnit, kOpXor, r1, r3); // r1 = r1 - r3 - CF |